Figure 48. Control Circuit In External Clock Mode 1; Figure 49. External Trigger Input Block - ST STM32F101 Series Reference Manual

Advanced control timer (TIM1)
For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = '01' in
the TIM1_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIM1_CCMR1
register (if no filter is needed, keep IC2F=0000).
3. Select rising edge polarity by writing CC2P=0 in the TIM1_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIM1_SMCR
register.
5. Select TI2 as the trigger input source by writing TS=110 in the TIM1_SMCR register.
6. Enable the counter by writing CEN=1 in the TIM1_CR1 register.
Note: The capture prescaler is not used for triggering, so you don't need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

Figure 48. Control circuit in external clock mode 1

External clock source mode 2
This mode is selected by writing ECE=1 in the TIM1_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 49

Figure 49. External trigger input block

ETR pin
162/501
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
gives an overview of the external trigger input block.
ETR
0
divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIM1_SMCR
TIM1_SMCR
TI2
34
TIF
Write TIF=0
ETRP
filter
downcounter
f
DTS
ETF[3:0]
TIM1_SMCR
35 36
ti2f or
or
ti1f or
encoder
mode
external clock
trgi
mode 1
ETRF external clock
mode 2
CK_INT
internal clock
mode
(internal clock)
ECE SMS[2:0]
TIM1_SMCR
RM0008
ck_psc