Spi Communication Using Dma (Direct Memory Addressing) - ST STM32F101 Series Reference Manual

RM0008
If data are present in the TX buffer, the CRC value is transmitted only after the transmission
of the data byte. During CRC transmission, the CRC calculator is switched off and the
register value remains unchanged.
Note: Please refer to the product specifications for availability of this feature.
SPI communication using CRC is possible through the following procedure:
Program the polynomial in the SPI_CRCPOLYR register
Enable CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This also
clears the SPI_RXCRCR and SPI_TXCRCR registers
Program the CPOL, CPHA, LSBfirst, DFF, BR, SSM, SSI and MSTR values
Enable the SPI by setting the SPE bit in SPI_CR1
Start the communication and sustain the communication until all but one byte or half-
word have been transmitted or received.
On writing the last byte or half-word to the TX buffer, set the CRCNext bit in the
SPI_CR1 register to indicate that after transmission of the last byte, the CRC should be
transmitted. CRC calculation is frozen during the CRC transmission.
After transmitting the last byte or half word, the SPI transmits the CRC. The CRCNEXT
bit is reset. The CRC is also received and compared against the SPI_RXCRCR value.
If the value does not match, the CRCERR flag in SPI_SR is set and an interrupt can be
generated when the ERRIE bit in the SPI_CR2 register is set.
Note: With high bit rate frequencies, the user must take care when transmitting CRC. As the
number of used CPU cycles has to be as low as possible in the CRC transfer phase, the
calling of software functions in the CRC transmission sequence is forbidden to avoid errors
in the last data and CRC reception.
For high bit rate frequencies, the DMA mode is advised to avoid degradation of SPI speed
performance due to CPU accesses impacting the SPI bandwidth.
18.3.7

SPI communication using DMA (direct memory addressing)

To operate at its maximum speed, the SPI needs to be fed with the data for transmission and
the data received on the RX buffer should be read to avoid overrun. To facilitate the
transfers, SPI is implemented with a DMA facility with a simple request/acknowledge
protocol. The DMA access is requested when the enable bit in the SPI_CR2 register is
enabled. There are separate requests for the TX buffer and the RX buffer.
Note: For high bitrate frequencies, the DMA mode is advised to avoid degradation of SPI speed
performance due to CPU accesses impacting the SPI bandwidth.
DMA capability with CRC
When SPI communication in full-duplex mode is enabled with the CRC communication and
the DMA mode, the transmission and reception of the CRC bytes at the end of
communication are done automatically.
At the end of data and CRC transfers, the flag CRCERR of SPI-SR is set if corruption occurs
during the transfer
Serial peripheral interface (SPI)
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