Figure 99. Capture/Compare Channel 1 Main Circuit; Figure 100. Output Stage Of Capture/Compare Channel (Channel 1) - ST STM32F101 Series Reference Manual

Advanced arm-based 32-bit mcus
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RM0008

Figure 99. Capture/compare channel 1 main circuit

read CCR1H
read CCR1L
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR

Figure 100. Output stage of capture/compare channel (channel 1)

ETRF
CNT > CCR1
CNT = CCR1 Controller
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
S
read_in_progress
Capture/Compare Preload Register
R
capture_transfer
input
mode
Capture/Compare Shadow Register
oc1ref
Output Mode
OC1M[2:0]
TIMx_CCMR1
APB Bus
MCU-peripheral interface
8
8
compare_transfer
capture
Counter
To the master mode
controller
General purpose timer (TIMx)
write CCR1H
S
write_in_progress
write CCR1L
R
CC1S[1]
output
mode
CC1S[0]
UEV
(from time
comparator
base unit)
CNT>CCR1
CNT=CCR1
0
Output
Enable
1
Circuit
CC1P
TIMx_CCER
CC1E TIMx_CCER
OC1PE
OC1PE
TIMx_CCMR1
OC1
229/501

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