ST STM32F101 Series Reference Manual page 60

Reset and clock control (RCC)
Bit 16 LSIRDYC LSI Ready Interrupt Clear
Set by software to clear LSIRDYF.
Reset by hardware when clear done.
0: LSIRDYF not cleared
1: LSIRDYF cleared
Bits 15:13 Reserved, always read as 0.
Bit 12 PLLRDYIE PLL Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE HSE Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the external 1-25 MHz oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE HSI Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator
stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE LSE Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the external 40 kHz oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE LSI Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by internal RC 40 kHz oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Bit 7 CSSF Clock Security System Interrupt flag
Reset by software by writing CSSC.
Set by hardware when a failure is detected in the external 1-25 MHz oscillator.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bits 6:5 Reserved, always read as 0.
Bit 4 PLLRDYF PLL Ready Interrupt flag
Reset by software by writing PLLRDYC.
Set by hardware when the PLL locks and PLLRDYDIE is set.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit3 HSERDYF HSE Ready Interrupt flag
Reset by software by writing HSERDYC.
Set by hardware when External Low Speed clock becomes stable and HSERDYDIE is set.
0: No clock ready interrupt caused by the external 1-25 MHz oscillator
1: Clock ready interrupt caused by the external 1-25 MHz oscillator
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