ST STM32F101 Series Reference Manual page 31

RM0008
Reading Flash memory
Flash memory instructions and data access are performed through the AHB bus. The
prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed
in the Flash memory interface, and priority is given to data access on the DCode bus.
Read accesses can be performed with the following configuration options:
Latency: number of wait states for a read operation programmed on-the-fly
Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be
replaced with a single read from the Flash memory as the size of the block matches the
bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is
possible as the CPU fetches one word at a time with the next word readily available in
the prefetch buffer
HalfCycle: for power optimization
Note: 1 These options should be used in accordance with the Flash memory access time. The wait
states represent the ratio of the SYSCLK (system clock) period to the Flash memory access
time:
zero wait state, if 0 < SYSCLK
one wait state, if 24 MHz < SYSCLK
two wait states, if 48 MHz < SYSCLK
2 Half cycle configuration is not available in combination with a prescaler on the AHB. The
clock system should be equal to the HCLK clock. This feature can therefore be used only
with a direct clock from the internal, 8 MHz RC (HSI) oscillator or with the HSE oscillator.
3 The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB
clock
4 Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode
instructions. The DMA provides one free cycle after each transfer. Some instructions can be
performed together with DMA transfer.
Programming and erasing Flash memory
The Flash memory can be programmed 16 bits (half words) at a time.
The Flash memory erase operation can be performed at page level or on the whole Flash
area (mass-erase). The mass-erase does not affect the information blocks.
To ensure that there is no over-programming, the Flash Programming and Erase Controller
blocks are clocked by a fixed clock.
The End of write operation (programming or erasing) can trigger an interrupt. This interrupt
can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the
interrupt is served only after an exit from WFI.
Note: For further information on Flash memory operations and register configurations, please refer
to the STM32F10xxx Flash programming manual.
≤
24 MHz
≤
48 MHz
≤
72 MHz
Memory and bus architecture
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