Sw-Ap Registers; Ahb-Ap (Ahb Access Port) - Valid For Both Jtag-Dp Or Sw-Dp - ST STM32F101 Series Reference Manual

Debug support (DBG)
Table 78.
A(3:2)
10 Write
11 Read/Write
20.8.6

SW-AP registers

Access to these registers are initiated when APnDP=1
There are many AP Registers (see AHB-AP) addressed as the combination of:
The shifted value A[3:2]
The current value of the DP SELECT register
20.9 AHB-AP (AHB Access Port) - valid for both JTAG-DP or SW-
DP
Features:
System access is independent of the processor status.
Either SW-DP or JTAG-DP accesses AHB-AP.
The AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the
data buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode
bus.
Bitband transactions are supported.
AHB-AP transactions bypass the FPB.
The address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes)
and consists of:
a)
b)
The AHB-AP of the Cortex-M3 includes 9 x 32-bits registers:
Table 79.
Address
offset
0x00
0x04
480/501
SW-DP registers (continued)
CTRLSEL bit
R/W of SELECT
register
Bits [8:4] = the bits[7:4] APBANKSEL of the DP SELECT register
Bits [3:2] = the 2 address bits of A(3:2) of the 35-bit packet request for SW-DP.
Cortex-M3 AHB-AP registers
Register name
AHB-AP Control and
Status Word
AHB-AP Transfer Address
Register
The purpose is to select the current access
SELECT
port and the active 4-words register window
This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
READ
transaction),
BUFFER
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction
Configures and controls transfers through the AHB
interface (size, hprot, status on current transfer, address
increment type
RM0008
Notes
Notes