Figure 28. Counter Timing Diagram, Internal Clock Divided By 1; Figure 29. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32F101 Series Reference Manual

Advanced control timer (TIM1)
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate doesn't change). In addition, if the URS bit (update request selection) in
TIM1_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM1_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIM1_RCR register,
The auto-reload shadow register is updated with the preload value (TIM1_ARR),
The buffer of the prescaler is reloaded with the preload value (content of the TIM1_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIM1_ARR=0x36.

Figure 28. Counter timing diagram, internal clock divided by 1

Figure 29. Counter timing diagram, internal clock divided by 2

152/501
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
31 32 33 34 35 36 00 01 02 03 04 05 06 07
0034
0035 0036 0000 0001 0002 0003
RM0008