Stop Mode; Table 6. Sleep-On-Exit - ST STM32F101 Series Reference Manual

RM0008
Table 6.
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
3.3.4

Stop mode

The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock
gating. The voltage regulator can be configured either in normal or low-power mode. In Stop
mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved.
Entering Stop mode
Refer to
To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the
(PWR_CR).
If Flash memory programming is ongoing, the Stop entry is delayed until the memory
access is finished.
If an access to APB domain is ongoing, Stop mode entry is delayed until the APB access is
finished.
In Stop mode, the following features can be selected by programming individual control bits:
Independent Watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 10.1
real-time clock (RTC): this is configured by the RTCEN bit in the
register (RCC_BDCR)
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the
register
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register
Exiting Stop mode
Refer to
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.
Sleep-on-exit
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex™-M3 System Control register.
Interrupt: refer to
None
Table 7 for details on how to enter Stop mode.
in Section 10: Independent watchdog
(RCC_CSR).
Table 7 for more details on how to exit Stop mode.
Description
Table 27: Vector table.
(IWDG).
(RCC_BDCR).
Power control (PWR)
Power control register
Backup domain control
Control/status
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