Combined Injected Simultaneous + Interleaved; Figure 155. Alternate + Regular Simultaneous; Figure 156. Case Of Trigger Occurring During Injected Conversion; Figure 157. Interleaved Single Channel With Injected Sequence Ch11, Ch12 - ST STM32F101 Series Reference Manual

Advanced arm-based 32-bit mcus

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Analog-to-digital converter (ADC)

If a trigger occurs during an injected conversion that has interrupted a regular conversion, it

will be ignored.

Combined injected simultaneous + interleaved

It is possible to interrupt an interleaved conversion with an injected event. In this case the

interleaved conversion is interrupted and the injected conversion starts, at the end of the

injected sequence the interleaved conversion is resumed.

using an example.

When the ADC clock prescaler is set to 4, the interleaved mode does not recover with

evenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6

ADC clock periods, instead of 7 clock periods followed by 7 clock periods.

shows the behavior in this case (2nd trig is ignored).

synchro not lost

shows the behavior

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