Rcc Register Description; Clock Control Register (Rcc_Cr) - ST STM32F101 Series Reference Manual

Reset and clock control (RCC)
programmed in alternate function mode. One of 4 clock signals can be selected as the MCO
clock.
SYSCLK
HSI
HSE
PLL clock divided by 2
The selection is controlled by the MCO[2:0] bits of the
(RCC_CFGR).
4.3

RCC register description

Refer to
4.3.1

Clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
31 30 29
Reserved
Res.
15 14 13
r r r
Bits 31:26 Reserved, always read as 0.
Bit 25 PLLRDY PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON PLL enable
Set and reset by software to enable PLL.
Reset by hardware when entering Stop and Standby mode. This bit can not be reset if the PLL clock
is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, always read as 0.
Bit 19 CSSON Clock Security System enable
Set and reset by software to enable clock detector.
0: Clock detector OFF
1: Clock detector ON if external 1-25 MHz oscillator is ready.
54/501
Section 1.1 on page 23
28 27 26 25
PLL
RDY
r
12 11 10 9
HSICAL[7:0]
r r r r
for a list of abbreviations used in register descriptions.
24 23 22
PLLON Reserved
rw Res.
8 7 6
HSITRIM[4:0]
r rw rw
Clock configuration register
21 20 19 18
CSS HSE
ON BYP
rw rw
5 4 3 2
Res.
rw rw rw
RM0008
17 16
HSE HSE
RDY ON
r rw
1 0
HSI
HSION
RDY
r rw