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4.3
MCR/MRC
ARM DDI0145B
These cycles look very similar to STC/LDC. An example, with a busy-wait state, is
shown in Figure 4-3:
First InMREQ is driven LOW to denote that the instruction on ID is entering the
decode stage of the pipeline. This causes the coprocessor to decode the new instruction
and drive CHSD[1:0] as required. In the next cycle InMREQ is driven LOW to denote
Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM9TDMI Coprocessor Interface
Figure 4-3 ARM9TDMI MCR / MRC transfer timing
4-9
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