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10. TIMING CHARACTERISTICS
10.4 Display Control I/O Timing
t
r
CL
FR
F1,F2
SYNC
Item
Use of built-in
oscillation circuit
F1 and F2 delay time
(CLS = HIGH)
External input
F1 and F2 delay time
(CLS = LOW)
Item
FR delay time
F1 and F2 delay time
SYNC delay time
Input clock duty ratio *2
Input clock cycle
Input clock rise time (20% to 80%) *3
Input clock fall time (20% to 80%) *3
Low level pulse width
High level pulse width
*1: All timings are stipulated on the basis of 20% and 80% of V
*2: The CL duty ratio is stipulated by
*3 A signal beyond the specification has no problem for the functionality, but
should be kept.
64
t
t
WHCL
WLCL
t
f
t
DSYNC
Table 10.4 Output timing
Signal Symbol
FR delay time
FR
F1,F2
SYNC delay time
SYNC
FR delay time
FR
F1,F2
SYNC delay time
SYNC
Table 10.5 Input Timing
Signal
FR
F1,F2
SYNC
CL
t
WHCL
t
=
CLD
t
CLF
t
t
CLF
DFR
t
DF1
Fig.10.4
Conditions
t
CL = 50pF
DFR
t
DF1,F2
t
DSYNC
t
DFR
t
DF1,F2
t
DSYNC
Symbol
Conditions
t
DFR
t
DF1,F2
t
DSYNC
t
CLD
t
CLF
t
r
t
f
t
WLCL
t
WHCL
.
DD
×
t
=
100
[%]
or
CLD
EPSON
S1D15722D01B000 Technical Manual (Rev.1.1)
,
F2
= -40 to +90 ° C]
[V
=3.0V to 5.5V, T
DD
a
Standard value
Min.
Typ.
-200
-
-200
-
-200
-
0
-
0
-
0
-
= -40 to +90 ° C]
[V
=3.0V to 5.5V, T
DD
a
Standard value
Min.
Typ.
-1.25
-
-1.25
-
-1.25
-
20
-
6.25
-
-
-
-
-
1.25
-
1.25
-
t
WLCL
×
100
[%]
.
t
CLF
t
t
t
,
and
CLF
WLCL
t
DSYNC
Unit
Max.
200
ns
200
200
500
500
500
Unit
Max.
µ s
1.25
µ s
1.25
µ s
1.25
80
%
µ s
-
15
ns
15
ns
µ s
-
µ s
-
always
WHCL
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