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CP r,i
Source Format:
Source Format:
Operation:
Operation:
OP-Code:
OP-Code:
Type:
Type:
Clock Cycles:
Clock Cycles:
Flag:
Flag:
Description:
Description:
Example:
Example:
CP r,q
Source Format:
Source Format:
Operation:
Operation:
OP-Code:
OP-Code:
Type:
Type:
Clock Cycles:
Clock Cycles:
Flag:
Flag:
Description:
Description:
Example:
Example:
S1C6200/6200A CORE CPU MANUAL
Compare immediate data i with r-register
CP r,i
r - i
to i
3
0
1 1 0 1 1 1 r
MSB
II
7
C –
Set if r < i
to i
; otherwise, reset.
3
0
Z –
Set if r = i
to i
; otherwise, reset.
3
0
D –
Not affected
I –
Not affected
Compares immediate data i to the r-register by subtracting i from the contents of r.
The r-register remains unchanged.
1. When Z = 0 and C = 0 then i < r
2. When Z = 1 and C = 0 then i = r
3. When Z = 0 and C = 1 then i > r
CP A,4
A register
0100
B register
1010
Memory (MX)
0010
C flag
1
Z flag
0
Compare q-register with r-register
CP r,q
r - q
1 1 1 1 0 0 0 0 r
MSB
IV
7
C –
Set if r < q; otherwise, reset.
Z –
Set if r = q; otherwise, reset.
D –
Not affected
I –
Not affected
Compares the q-register to the r-register by subtracting the contents of q from the
contents of r. The registers remain unchanged.
1. When Z = 0 and C = 0 then q < r
2. When Z = 1 and C = 0 then q = r
3. When Z = 0 and C = 1 then q > r
CP A,B
A register
1000
B register
0100
Memory (MY)
0111
C flag
0
Z flag
0
r
i
i
i
i
1
0
3
2
1
0
LSB
CP MX,7
0100
1010
0010
0
1
r
q
q
1
0
1
0
LSB
CP MY,A
1000
0100
0111
0
0
EPSON
3 INSTRUCTION SET
DC0H to DFFH
CP B,2
0100
0100
1010
1010
0010
0010
1
0
0
0
F00H to F0FH
1000
0100
0111
1
0
35
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