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4.11.2.6 Transfer rate setting for serial interface
The signal that is made from underflows of timer 1 by dividing them in 1/2, can be used as the clock
source for the serial interface.
The programmable timer outputs the clock to the serial interface by setting timer 1 into RUN state
(PTRUN1 = "1"). It is not necessary to control with the PTOUT register.
PTRUN1
Timer 1 underflow
Source clock for serial I/F
A setting value for the RLD1X register according to a transfer rate is calculated by the following expres-
sion:
RLD1X = fosc / (2 ∗ bps ∗ division ratio of the prescaler) - 1
fosc: Oscillation frequency (OSC1/OSC3)
bps: Transfer rate
(00H can be set to RLD1X)
4.11.3 One channel × 16-bit timer (MODE16 = "1") operation
Timer 0 and timer 1 are chained together to form 16-bit down counter low byte in timer 0, high byte in
timer 1.
4.11.3.1 Setting of initial value and counting down
Timers 0 and 1 each have a down counter and reload data register.
The reload data registers RLD00–RLD07 (timer 0) and RLD10–RLD17 (timer 1) are used to set the initial
value to the down counter.
By writing "1" to the timer reset bit PTRST0 (timer 0) or PTRST1 (timer 1), the down counter loads the
initial value set in the reload register RLD. Therefore, down-counting is executed from the stored initial
value by the input clock.
The register PTRUN0 (timer 0) is used to control the RUN/STOP for timers 0 and 1. By writing "1" to the
register after presetting the reload data to the down counter, the down counter starts counting down.
Writing "0" stops the input count clock and the down counter stops counting. This control (RUN/STOP)
does not affect the counter data. The counter maintains its data while stopped, and can restart counting
continuing from that data.
The counter data can be read via the data buffers PTD00–PTD07 (timer 0) and PTD10–PTD17 (timer 1) in
optional timing. However, the counter has the data hold function the same as the clock timer, that holds
the high-order data when the low-order data is read in order to prevent the borrowing operation between
low- and high-order reading, therefore be sure to read the low-order data first.
The counter reloads the initial value set in the reload data register RLD when an underflow occurs
through the count down. It continues counting down from the initial value after reloading.
In addition to reloading the counter, this underflow signal controls the interrupt generation, pulse (TOUT
signal) output and clock supplying to the serial interface.
S1C63358 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmable Timer)
Fig. 4.11.2.6.1 Synchronous clock of serial interface
EPSON
81
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