Figure 3-3: Typical System Diagram (Mc68K Bus 1, 16-Bit 68000); Figure 3-4: Typical System Diagram (Mc68K Bus 2, 32-Bit 68030) - Epson S1D13505 Technical Manual

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MC68000
BUS
A[23:21]
FC0, FC1
A[20:1]
D[15:0]
LDS#
UDS#
AS#
R/W#
DTACK#
BCLK
RESET#
MC68030
BUS
A[31:21]
FC0, FC1
A[20:0]
D[31:16]
DS#
AS#
R/W#
SIZ1
SIZ0
DSACK1#
BCLK
RESET#
S1D13505
X23A-A-001-14
Power
Management
M/R#
Decoder
CS#
Decoder
AB[20:1]
DB[15:0]
S1D13505F00A
AB0#
WE1#
BS#
RD/WR#
WAIT#
BUSCLK
RESET#

Figure 3-3: Typical System Diagram (MC68K Bus 1, 16-Bit 68000)

Power
Management
M/R#
Decoder
CS#
Decoder
AB[20:0]
DB[15:0]
WE1#
BS#
S1D13505F00A
RD/WR#
RD#
WE0#
WAIT#
BUSCLK
RESET#

Figure 3-4: Typical System Diagram (MC68K Bus 2, 32-Bit 68030)

.
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
RED,GREEN,BLUE
HRTC
VRTC
IREF
256Kx16
FPM/EDO-DRAM
.
Oscillator
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
RED,GREEN,BLUE
HRTC
VRTC
IREF
256Kx16
FPM/EDO-DRAM
Epson Research and Development
Vancouver Design Center
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
Display
FPFRAME
FPLINE
MOD
CRT
Display
IREF
UD[7:0]
LD[7:0]
4/8/16-bit
FPSHIFT
LCD
FPFRAME Display
FPLINE
MOD
CRT
Display
IREF
Hardware Functional Specification
Issue Date: 01/02/02