NEC Univerge SV8500 Operation And Maintenance Manual page 84

PIR 3
MUX
PIR 2
MUX
PIR 1
MUX
PIR 0
MUX
(Note 3)
Circuit cards shown in dotted line are in STBY mode.
Note 1:
When the CPU ACT/STBY is changed over, GT will also be changed over in TSWR.
Note 2:
IOC card is option.
Note 3:
Figure 1-17 CPU Controlling Block Diagram (4-IMG)
IMG0
PM BUS
LC/TRK LC/TRK
MUX
PM BUS
PM BUS
LC/TRK LC/TRK
MUX
PM BUS
PM BUS
LC/TRK LC/TRK
MUX
PM BUS
PM BUS
LC/TRK LC/TRK
MUX
PM BUS
TSWR
BUS0
GT 0
GT 1
BUS1
GT :PH-GT09
TSW :PH-SW12
DLKC:PH-PC20
PLO :PH-CK16-D
MUX :PH-PC36
PIR 3
MUX
PIR 2
MUX
PIR 1
MUX
PIR 0
MUX
To IMG 2 To IMG 3
MUX
M M M M M M M M
/INT
U U U U U U U U
X X X X X X X X
TSW
003 002 001 000 013 012 011 010
02
MUX/INT MUX/INT
TSW 00 TSW 01
Local I/O BUS
DLKC BUS
DLKC 0
DLKC BUS
Local I/O BUS
Local I/O BUS
[Symbols]
: CPU Controlling Routes
: Circuit Card (ACT)
: External Cable
: Signal
– 37 –
CHAPTER 1
IMG1
PM BUS
LC/TRK LC/TRK
MUX
PM BUS
PM BUS
LC/TRK LC/TRK
MUX
PM BUS
PM BUS
LC/TRK LC/TRK
MUX
PM BUS
PM BUS
LC/TRK LC/TRK
MUX
PM BUS
To IMG 2 To IMG 3
MUX MUX
M M M M M M M M
/INT /INT
U U U U U U U U
X X X X X X X X
TSW TSW
100 101 102 103 110 111 112 113
03 12
MUX/INT MUX/INT
TSW 10 TSW 11
Local I/O BUS
DLKC BUS
DLKC 1
DLKC 1
DLKC BUS
PLO 0 PLO 1
: Cable
: Circuit Card (STBY)
: Clock Oscillator
General
MUX
/INT
TSW
13