NEC Univerge SV8500 Operation And Maintenance Manual page 686

Figure 5-18 CPU Controlling Block Diagram (4-IMG)
IMG0
PIR 3
PM BUS
MUX
LC/TRK
PM BUS
PIR 2
PM BUS
MUX
LC/TRK
PM BUS
PIR 1
PM BUS
MUX
LC/TRK
PM BUS
PIR 0
PM BUS
MUX
LC/TRK
PM BUS
CHAPTER 5
LC/TRK
MUX
LC/TRK
MUX
LC/TRK
MUX
LC/TRK
MUX
TSWR
M
U
X
003
MUX/INT
BUS0
GT 0
GT 1
BUS1
GT : PH-GT09
TSW : PH-SW12
DLKC: PH-PC20
PLO : PH-CK16-D, etc.
MUX : PH-PC36
– 639 –
Operation Procedure for System with PIR
IMG1
PIR 3
PM BUS
MUX
LC/TRK
PM BUS
PIR 2
PM BUS
MUX
LC/TRK
PM BUS
PIR 1
PM BUS
MUX
LC/TRK
PM BUS
PIR 0
PM BUS
MUX
LC/TRK
PM BUS
To IMG 2 To IMG 3
MUX MUX
M M M M M M M M
/INT /INT
U U U U U U U U
X X X X X X X X
TSW TSW
002 001 000 013 012 011 010 100
02 03
MUX/INT MUX/INT
TSW 00 TSW 01
Local I/O BUS
DLKC BUS
DLKC 0
DLKC BUS
Local I/O BUS
PLO 0
Local I/O BUS
Symbols:
: CPU Controlling Routes
: Circuit Card (ACT)
: External Cable
: Signal
LC/TRK
MUX
LC/TRK
MUX
LC/TRK
MUX
LC/TRK
MUX
To IMG 2 To IMG 3
MUX MUX
M M M M M M M
/INT /INT
U U U U U U U
X X X X X X X
TSW TSW
101 102 103 110 111 112 113
12 13
MUX/INT
TSW 10 TSW 11
Local I/O BUS
DLKC BUS
DLKC 1
DLKC 1
DLKC BUS
PLO 1
: Cable
: Circuit Card (STBY)
: Clock Oscillator