Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3) - NEC V850E/IA1 mPD703116 User Manual

32-bit single-chip microcontrollers

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6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)

These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from on-chip

peripheral I/O.

The interrupt requests set with these registers serve as DMA transfer start factors.

These registers can be read/written in 8-bit units. However, only bit 7 (DFn) can be read/written in 1-bit units (n = 0

Be sure to set bit 6 to 0. If it is set to 1, the operation is not guaranteed.

Cautions 1. Be sure to stop DMA operation before making changes to DTFRn register settings.

2. An interrupt request input in a standby mode (IDLE or software STOP mode) cannot be used

as a DMA transfer start factor except for INTP0 to INTP6 and INTP20 to INTP25 (when the

noise elimination by analog filter is selected).

Bit Position

Remark n = 0 to 3

CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)

This is a DMA transfer request flag.

Only 0 can be written to this flag.

0: No DMA transfer request

1: DMA transfer request

If an interrupt that causes DMA transfer occurs while DMA transfer is disabled (including if

it has been suspended by an NMI or forcibly terminated by software), and if this DMA

transfer request must be cleared, stop the operation causing the interrupt (e.g., disable

reception if serial reception is in progress), and then clear the DFn bit. If it is clear in the

application that the interrupt will not occur again until DMA transfer is resumed next, it is

not necessary to stop the operation causing the interrupt.

Sets the interrupt source that serves as the DMA transfer start factor.

User's Manual U14492EJ3V0UD

DMA request from on-chip

peripheral I/O disabled

Initial value

Interrupt Source