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NEC mPD780058 Series Preliminary User's Manual

8-bit single-chip microcontrollers

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Preliminary User's Manual

µ PD780058, 780058Y Subseries

8-bit Single-chip Microcontrollers

µ PD780053

µ PD780054

µ PD780055

µ PD780056

µ PD780058

µ PD78F0058

Document No.

U12013EJ2V0UM00 (2nd edition)

Date Published February 1998 N CP (K)

©

1997

Printed in Japan

µ PD780053Y

µ PD780054Y

µ PD780055Y

µ PD780056Y

µ PD780058Y

µ PD78F0058Y

1

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Summary of Contents for NEC mPD780058 Series

Page 1 Preliminary User’s Manual µ PD780058, 780058Y Subseries 8-bit Single-chip Microcontrollers µ PD780053 µ PD780053Y µ PD780054 µ PD780054Y µ PD780055 µ PD780055Y µ PD780056 µ PD780056Y µ PD780058 µ PD780058Y µ PD78F0058 µ PD78F0058Y Document No. U12013EJ2V0UM00 (2nd edition) Date Published February 1998 N CP (K) ©...
Page 2 [MEMO]...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. FIP, EEPROM, and IEBus are trademarks of NEC Corporation. Windows and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Main Revisions in This Edition Page Description pp. 127 to 131, 137 Change of following block diagrams of ports: Figures 6-5 and 6-7 P20, P21, and P23 to P26 Block Diagram, Figure 6-6 and 6-8 P22 and P27 Block diagram, Figure 6-9 P30 to P37 Block Diagram, and Figure 6-16 P71 and P72 Block Diagram pp.
Page 7 PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the µ PD780058 and 780058Y Subseries and design and develop its application systems and programs. Purpose This manual is intended for users to understand the functions described in the organization below.
Page 8 Chapter Organization: This manual divides the descriptions for the µ PD780058 and 780058Y Subseries into different chapters as shown below. Read only the chapters related to the device you use. µ PD780058 µ PD780058Y Chapter Subseries Subseries Outline ( µ PD780058 Subseries) √...
Page 9 Differences Between µ PD780058 and µ PD780058Y Subseries: The µ PD780058 and µ PD780058Y Subseries are different in the following functions of the serial interface channel 0. µ PD780058 µ PD780058Y Modes of serial interface channel 0 Subseries Subseries √ √...
Page 10 Development Tool Documents (User’s Manuals) Document name Document No. English Japanese RA78K0 Assembler Package Operation U11802E U11802J Assembly Language U11801E U11801J Structured Assembly Language U11789E U11789J RA78K Series Structured Assembler Preprocessor EEU-1402 U12323J CC78K/0 C Compiler Operation U11517E U11517J Language U11518E U11518J CC78K/0 C Compiler Application Note...
Page 11 English Japanese IC PACKAGE MANUAL C10943X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
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Page 13: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ( µ PD780058 Subseries) ................Features ..........................Applications ........................Ordering Information ......................Pin Configuration (Top View) ................... 78K/0 Series Line-up ......................Block Diagram ........................Outline of Function ......................Mask Options ........................CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) ................Features ..........................
Page 14 CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) ..............Pin Function List ....................... Description of Pin Functions ................... 4.2.1 P00 to P05, P07 (Port 0) ..................... 4.2.2 P10 to P17 (Port 1) ......................4.2.3 P20 to P27 (Port 2) ......................4.2.4 P30 to P37 (Port 3) ......................
Page 15 5.4.6 Register indirect addressing ....................5.4.7 Based addressing ........................ 5.4.8 Based indexed addressing ....................5.4.9 Stack addressing ......................... CHAPTER 6 PORT FUNCTIONS ....................Port Functions ........................Port Configuration ......................6.2.1 Port 0 ........................... 6.2.2 Port 1 ........................... Port 2 ( µ PD780058 Subseries) .................... 6.2.3 Port 2 ( µ...
Page 16 8.5.1 Interval timer operations ...................... 8.5.2 PWM output operations ....................... 8.5.3 PPG output operations ......................8.5.4 Pulse width measurement operations ................. 8.5.5 External event counter operation ..................8.5.6 Square-wave output operation .................... 8.5.7 One-shot pulse output operation ..................16-Bit Timer/Event Counter Operating Cautions ............CHAPTER 9 8-BIT TIMER/EVENT COUNTER ................
Page 17 14.2 A/D Converter Configuration ................... 14.3 A/D Converter Control Registers ..................14.4 A/D Converter Operations ....................14.4.1 Basic operations of A/D converter ..................14.4.2 Input voltage and conversion results ................... 14.4.3 A/D converter operating mode ..................... 14.5 A/D Converter Cautions ....................CHAPTER 15 D/A CONVERTER .......................
Page 18 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 ................19.1 Serial Interface Channel 2 Functions ................19.2 Serial Interface Channel 2 Configuration ............... 19.3 Serial Interface Channel 2 Control Registers ..............19.4 Serial Interface Channel 2 Operation ................19.4.1 Operation stop mode ......................19.4.2 Asynchronous serial interface (UART) mode (with time-division transfer function) .....
Page 19 25.2 ROM Correction Configuration ..................25.3 ROM Correction Control Registers ................. 25.4 ROM Correction Application .................... 25.5 ROM Correction Usage Example ..................25.6 Program Execution Flow ....................25.7 ROM Correction Cautions ....................CHAPTER 26 µ PD78F0058, 78F0058Y ..................... 26.1 Memory Size Switching Register ..................26.2 Internal Expansion RAM Size Switching Register ............
Page 20 LIST OF FIGURES (1/8) Figure No. Title Page 3-1. Pin Input/Output Circuit List ....................4-1. Pin Input/Output Circuit List ....................Memory Map ( µ PD780053, 780053Y) ................5-1. Memory Map ( µ PD780054, 780054Y) ................5-2. Memory Map ( µ PD780055, 780055Y) ................5-3.
Page 21 LIST OF FIGURES (2/8) Figure No. Title Page 6-22. Key Return Mode Register Format ..................7-1. Clock Generator Block Diagram ..................7-2. Subsystem Clock Feedback Resistor ................. 7-3. Processor Clock Control Register Format ................7-4. Oscillation Mode Selection Register Format ..............7-5.
Page 22 LIST OF FIGURES (3/8) Figure No. Title Page 8-25. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) ..............8-26. Control Register Settings in External Event Counter Mode ..........8-27. External Event Counter Configuration Diagram ..............8-28.
Page 23 LIST OF FIGURES (4/8) Figure No. Title Page 12-3. Timer Clock Select Register 0 Format ................12-4. Port Mode Register 3 Format ..................... 13-1. Buzzer Output Control Circuit Block Diagram ..............13-2. Timer Clock Select Register 2 Format ................13-3. Port Mode Register 3 Format .....................
Page 24 LIST OF FIGURES (5/8) Figure No. Title Page 16-22. ACKT Operation ......................... 16-23. ACKE Operations ....................... 16-24. ACKD Operations ....................... 16-25. BSYE Operation ......................... 16-26. Pin Configuration ........................ 16-27. Address Transmission from Master Device to Slave Device (WUP = 1) ......16-28.
Page 25 LIST OF FIGURES (6/8) Figure No. Title Page 17-29. Logic Circuit of SCL Signal ....................18-1. Serial Interface Channel 1 Block Diagram ................. 18-2. Timer Clock Select Register 3 Format ................18-3. Serial Operation Mode Register 1 Format ................18-4. Automatic Data Transmit/Receive Control Register Format ..........
Page 26 LIST OF FIGURES (7/8) Figure No. Title Page 19-13. 3-wire Serial I/O Mode Timing .................... 19-14. Circuit of Switching in Transfer Bit Order ................19-15. Reception Completion Interrupt Request Generation Timing (When ISRM = 1) ....19-16. Receive Buffer Register Read Disable Period ..............20-1.
Page 27 LIST OF FIGURES (8/8) Figure No. Title Page 23-3. HALT Mode Release by RESET Input ................23-4. STOP Mode Release by Interrupt Request Generation ............. 23-5. STOP Mode Release by RESET Input ................24-1. Reset Function Block Diagram ................... 24-2. Reset Timing by RESET Input ....................
Page 28 LIST OF TABLES (1/3) Table No. Title Page 1-1. Mask Options of Mask ROM Versions ................2-1. Mask Options of Mask ROM Versions ................3-1. Pin Input/Output Circuit Types .................... 4-1. Pin Input/Output Circuit Types .................... 5-1. Vector Table ........................5-2.
Page 29 LIST OF TABLES (2/3) Table No. Title Page 10-1. Interval Timer Interval Time ....................10-2. Watch Timer Configuration ....................10-3. Interval Timer Interval Time ....................11-1. Watchdog Timer Program Runaway Detection Times ............11-2. Interval Times ........................11-3. Watchdog Timer Configuration ................... 11-4.
Page 30 LIST OF TABLES (3/3) Table No. Title Page 21-1. Interrupt Source List ......................21-2. Various Flags Corresponding to Interrupt Request Sources ..........21-3. Times from Maskable Interrupt Request Generation to Interrupt Service ......21-4. Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing ....... 21-5.
Page 31: Chapter 1 Outline ( Μ Pd780058 Subseries)
CHAPTER 1 OUTLINE ( µ PD780058 Subseries) 1.1 Features On-chip high-capacity ROM and RAM Item Program Memory Data Memory Mask ROM Flash Memory Internal High- Internal Buffer Internal Expansion RAM Part Number Speed RAM µ PD780053 24 Kbytes — 1,024 bytes 32 bytes None µ...
Page 32: Applications
80-pin plastic TQFP (Fine pitch) (12 × 12 mm) Flash memory Caution The µ PD780053GC, 780054GC, 780055GC, 780056GC, 780058GC, and 78F0058GC are available in two packages. For the package that can be supplied, consult an NEC sales representative. Remark ××× indicates ROM code suffix.
Page 33: Pin Configuration (Top View)
CHAPTER 1 OUTLINE ( µ PD780058 Subseries) 1.4 Pin Configuration (Top View) • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) µ PD780053GC-×××-3B9, 780054GC-×××-3B9, 780055GC-×××-3B9, µ PD780056GC-×××-3B9, 780058GC-×××-3B9, 78F0058GC-3B9 • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) µ...
Page 34 CHAPTER 1 OUTLINE ( µ PD780058 Subseries) A8 to A15 Address Bus Programmable Clock AD0 to AD7 Address/Data Bus Read Strobe ANI0 to ANI7 Analog Input RESET Reset ANO0, ANO1 Analog Output RTP0 to RTP7 Real-Time Output Port ASCK Asynchronous Serial Clock RxD0, RxD1 Receive Data ASTB...
Page 35: Series Line-Up
CHAPTER 1 OUTLINE ( µ PD780058 Subseries) 1.5 78K/0 Series Line-up 78K/0 Series product line-up is illustrated below. Part numbers in the boxes indicate subseries names. Products in mass production Products under development Y subseries products are compatible with I C bus.
Page 36 CHAPTER 1 OUTLINE ( µ PD780058 Subseries) The following lists the main functional differences between subseries products. Function Timer Serial Interface 8-bit 10-bit 8-bit MIN. External Capacity 8-bit 16-bit Watch WDT A/D A/D Value Expansion Subseries Name µ PD78075B √ Control 32K to 40K 4 ch 1 ch 1 ch 1 ch 8 ch –...
Page 37: Block Diagram
CHAPTER 1 OUTLINE ( µ PD780058 Subseries) 1.6 Block Diagram TO0/P30 P01 to P05 PORT 0 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 P10 to P17 PORT 1 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 P20 to P27 PORT 2 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34...
Page 38: Outline Of Function
CHAPTER 1 OUTLINE ( µ PD780058 Subseries) 1.7 Outline of Function µ PD780053 µ PD780054 µ PD780055 µ PD780056 µ PD780058 µ PD78F0058 Part Number Item Internal Mask ROM Flash memory memory 24 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes 60 Kbytes Note 1...
Page 39 CHAPTER 1 OUTLINE ( µ PD780058 Subseries) Part Number µ PD780053 µ PD780054 µ PD780055 µ PD780056 µ PD780058 µ PD78F0058 Item Vectored Maskable Internal: 13 interrupt External: 6 source Non-maskable Internal: 1 Software Test input Internal: 1 External: 1 Supply voltage = 1.8 to 5.5 V Operating ambient temperature...
Page 40: Mask Options
CHAPTER 1 OUTLINE ( µ PD780058 Subseries) 1.8 Mask Options The mask ROM versions ( µ PD780053, 780054, 780055, 780056, 780058) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production.
Page 41: Chapter 2 Outline ( Μ Pd780058Y Subseries)
CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) 2.1 Features On-chip high-capacity ROM and RAM Item Program Memory Data Memory Mask ROM Flash Memory Internal High- Internal Buffer Internal Expansion RAM Part Number Speed RAM µ PD780053Y 24 Kbytes — 1,024 bytes 32 bytes None µ...
Page 42: Applications
80-pin plastic TQFP (Fine pitch) (12 12 mm) Flash-memory Note Under planning Caution The µ PD780053YGC, 780054YGC, 780055YGC, 780056YGC, 780058YGC, and 78F0058YGC are available in two packages. For the package that can be supplied, consult an NEC sales representative. Remark ××× indicates ROM code suffix.
Page 43: Pin Configuration (Top View)
CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) 2.4 Pin Configuration (Top View) • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 2.7 mm) Note µ PD780053YGC-×××-3B9, 780054YGC-×××-3B9, 780055YGC-×××-3B9, µ PD780056YGC-×××-3B9, 780058YGC-×××-3B9, 78F0058YGC-3B9 • 80-pin plastic QFP (14 × 14 mm, Resin thickness: 1.4 mm) Note µ...
Page 44 CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) A8 to A15 Address Bus Read Strobe AD0 to AD7 Address/Data Bus RESET Reset ANI0 to ANI7 Analog Input RTP0 to RTP7 Real-Time Output Port ANO0, ANO1 Analog Output RxD0, RxD1 Receive Data ASCK Asynchronous Serial Clock SB0, SB1...
Page 45: Series Line-Up
CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) 2.5 78K/0 Series Line-up 78K/0 Series product line-up is illustrated below. Part numbers in the boxes indicate subseries names. Products in mass production Products under development Y subseries products are compatible with I C bus.
Page 46 CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) Major functional differences among the Y subseries are shown below. Function Serial Interface Configuration Subseries Name Capacity MIN. Value µ PD78078Y Control 48 K to 60 K 3-wire/2-wire/I : 1 ch 1.8 V µ...
Page 47: Block Diagram
CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) 2.6 Block Diagram TO0/P30 P01 to P05 PORT 0 16-bit TIMER/ TI00/INTP0/P00 EVENT COUNTER TI01/INTP1/P01 P10 to P17 PORT 1 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 P20 to P27 PORT 2 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34...
Page 48: Outline Of Function
CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) 2.7 Outline of Function µ PD780053Y µ PD780054Y µ PD780055Y µ PD780056Y µ PD780058Y µ PD78F0058Y Part Number Item Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Mask ROM Flash memory Internal memory...
Page 49 CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) µ PD780053Y µ PD780054Y µ PD780055Y µ PD780056Y µ PD780058Y µ PD78F0058Y Part Number Item Note Note Note Note Note Note Vectored Maskable Internal: 13 interrupt External: 6 source Non-maskable Internal: 1 Software Test input Internal: 1 External: 1...
Page 50: Mask Options
CHAPTER 2 OUTLINE ( µ PD780058Y Subseries) 2.8 Mask Options The mask ROM versions ( µ PD780053Y, 780054Y, 780055Y, 780056Y, 780058Y) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for the device production.
Page 51: Chapter 3 Pin Function ( Μ Pd780058 Subseries)
CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) 3.1 Pin Function List (1) Port pins (1/2) Pin Name Function After Reset Alternate Function Input/Output Input Port 0 Input only Input INTP0/TI00 7-bit input/output port Input/ Input/output mode can be specified Input INTP1/TI01 output...
Page 52 CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) (1) Port pins (2/2) Pin Name Function After Reset Alternate Function Input/Output P40 to P47 Input/ Port 4 Input AD0 to AD7 output 8-bit input/output port Input/output mode can be specified in 8-bit units. If used as an input port, an on-chip pull-up resistor can be used by software.
Page 53 CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) (2) Non-port pins (1/2) Pin Name Function After Reset Alternate Function Input/Output INTP0 Input External interrupt request inputs with specifiable valid edges (rising Input P00/TI00 edge, falling edge, both rising and falling edges). INTP1 P01/TI01 INTP2...
Page 54 CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) (2) Non-port pins (2/2) Pin Name Function After Reset Alternate Function Input/Output AD0 to AD7 Low-order address/data bus when expanding external memory Input P40 to P47 Input/output A8 to A15 Output High-order address bus when expanding external memory Input P50 to P57 Output...
Page 55: Description Of Pin Functions
CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) 3.2 Description of Pin Functions 3.2.1 P00 to P05, P07 (Port 0) This is a 7-bit input/output port. Besides serving as an input/output port, it functions as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation.
Page 56: P10 To P17 (Port 1)
Serial data input/output pins of serial interface (b) SCK0 and SCK1 Serial clock input/output pins of serial interface (c) SB0 and SB1 NEC standard serial bus interface input/output pins (d) BUSY Automatic transmit/receive busy input pins of serial interface (e) STB...
Page 57: P30 To P37 (Port 3)
CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) 3.2.4 P30 to P37 (Port 3) This is an 8-bit input/output port. Beside serving as an input/output port, it functions as timer input/output, clock output and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode This port functions as an 8-bit input/output port.
Page 58: P50 To P57 (Port 5)
CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) 3.2.6 P50 to P57 (Port 5) This is an 8-bit input/output port. Besides serving as an input/output port, it functions as an address bus. Port 5 can drive LEDs directly. The following operating modes can be specified bit-wise. (1) Port mode This port functions as an 8-bit input/output port.
Page 59: P70 To P72 (Port 7)
CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) 3.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise.
Page 60: P130 And P131 (Port 13)
CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) 3.2.10 P130 and P131 (Port 13) This is a 2-bit input/output port. Besides serving as an input/output port, it is used for a D/A converter analog output. The following operating modes can be specified bit-wise. (1) Port mode This port functions as a 2-bit input/output port.
Page 61: Vss0 , Vss1
CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) 3.2.18 V is the ground potential pin for ports. is the ground potential pin for blocks other than port and analog blocks. 3.2.19 V (Flash memory version only) High-voltage apply pin for flash memory programming mode setting and program write/verify. Connect directly to V pin in normal operating mode.
Page 62: Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) 3.3 Input/output Circuits and Recommended Connection of Unused Pins Table 3-1 shows the input/output circuit types of pins and the recommended connection of for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1.
Page 63 CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) Table 3-1. Pin Input/Output Circuit Types (2/2) Input/Output Pin Name Input/Output Recommended Connection of Unused Pins Circuit Type P60 to P63 (Mask ROM version) 13-J Input/output Connect independently via a resistor to V P60 to P63 (Flash memory version) 13-K P64/RD...
Page 64 CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) Figure 3-1. Pin Input/Output Circuit List (1/2) Type 2 Type 8-C pullup P-ch enable data P-ch IN/OUT Schmitt-Triggered Input with Hysteresis Characteristics output N-ch disable Type 10-B Type 5-H pullup pullup P-ch P-ch enable enable...
Page 65 CHAPTER 3 PIN FUNCTION ( µ PD780058 Subseries) Figure 3-1. Pin Input/Output Circuit List (2/2) Type 12-C Type 13-K IN/OUT pullup P-ch enable data N-ch output disable data P-ch IN/OUT output N-ch P-ch disable input P-ch medium breakdown enable analog output input buffer voltage N-ch...
Page 66 [MEMO]...
Page 67: Chapter 4 Pin Function ( Μ Pd780058Y Subseries)
CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) 4.1 Pin Function List (1) Port pins (1/2) Pin Name Function After Reset Alternate Function Input/Output Input Port 0 Input only Input INTP0/TI00 7-bit input/output port Input/ Input/output mode can be specified INTP1/TI01 output bit-wise.
Page 68 CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) (1) Port pins (2/2) Pin Name Function After Reset Alternate Function Input/Output P40 to P47 Input/ Port 4 Input AD0 to AD7 output 8-bit input/output port Input/output mode can be specified in 8-bit units. If used as an input port, an on-chip pull-up resistor can be used by software.
Page 69 CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) (2) Non-port pins (1/2) Pin Name Function After Reset Alternate Function Input/Output INTP0 Input External interrupt request inputs with specifiable valid edges (rising Input P00/TI00 edge, falling edge, both rising and falling edges). INTP1 P01/TI01 INTP2...
Page 70 CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) (2) Non-port pins (2/2) Pin Name Function After Reset Alternate Function Input/Output AD0 to AD7 Low-order address/data bus when expanding external memory Input P40 to P47 Input/output A8 to A15 Output High-order address bus when expanding external memory Input P50 to P57 Output...
Page 71: Description Of Pin Functions
CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) 4.2 Description of Pin Functions 4.2.1 P00 to P05, P07 (Port 0) This is a 7-bit input/output port. Besides serving as an input/output port, it functions as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation.
Page 72: P10 To P17 (Port 1)
CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) 4.2.2 P10 to P17 (Port 1) This is an 8-bit input/output port. Besides serving as an input/output port, it functions as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) Port mode This port functions as an 8-bit input/output port.
Page 73: P30 To P37 (Port 3)
CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) 4.2.4 P30 to P37 (Port 3) This is an 8-bit input/output port. Beside serving as an input/output port, it functions as timer input/output, clock output, and buzzer output. The following operating modes can be specified bit-wise. (1) Port mode This port functions as an 8-bit input/output port.
Page 74: P40 To P47 (Port 4)
CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) 4.2.5 P40 to P47 (Port 4) This is an 8-bit input/output port. Besides serving as an input/output port, it functions as an address/data bus. The test input flag (KRIF) can be set to 1 by detecting a falling edge. The following operating modes can be specified in 8-bit units.
Page 75: P70 To P72 (Port 7)
CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) 4.2.8 P70 to P72 (Port 7) This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. The following operating modes can be specified bit-wise.
Page 76: P130 And P131 (Port 13)
CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) 4.2.10 P130 and P131 (Port 13) This is a 2-bit input/output port. Besides serving as an input/output port, it is used for a D/A converter analog output. The following operating modes can be specified bit-wise. (1) Port mode This port functions as a 2-bit input/output port.
Page 77: Vss0 , Vss1
CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) 4.2.18 V is the ground potential pin for ports. is the ground potential pin for blocks other than port and analog blocks. 4.2.19 V (Flash memory version only) High-voltage apply pin for flash memory programming mode setting and program write/verify. Connect directly to V pin in normal operating mode.
Page 78: Input/Output Circuits And Recommended Connection Of Unused Pins
CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) 4.3 Input/Output Circuits and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended connection of unused pins. Refer to Figure 4-1 for the configuration of the input/output circuit of each type. Table 4-1.
Page 79 CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) Table 4-1. Pin Input/Output Circuit Types (2/2) Input/Output Pin Name Input/Output Recommended Connection of Unused Pins Circuit Type P60 to P63 (Mask ROM version) 13-J Input/output Connect independently via a resistor to V P60 to P63 (Flash memory version) 13-K Input/output...
Page 80 CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) Figure 4-1. Pin Input/Output Circuit List (1/2) Type 2 Type 8-C pullup P-ch enable data P-ch IN/OUT Schmitt-Triggered Input with Hysteresis Characteristics output N-ch disable Type 10-B Type 5-H pullup pullup P-ch P-ch enable enable...
Page 81 CHAPTER 4 PIN FUNCTION ( µ PD780058Y Subseries) Figure 4-1. Pin Input/Output Circuit List (2/2) Type 12-C Type 13-K IN/OUT pullup P-ch enable data N-ch output disable data P-ch IN/OUT output N-ch P-ch disable input P-ch medium breakdown enable analog output input buffer voltage N-ch...
Page 82 [MEMO]...
Page 83: Chapter 5 Cpu Architecture
CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces Figures 5-1 to 5-6 show memory maps. Figure 5-1. Memory Map ( µ PD780053, 780053Y) FFFFH Special Function Registers (SFRs) 256 × 8 bits FF00H FEFFH General Registers 32 × 8 bits FEE0H FEDFH Internal High-speed RAM 1,024 ×...
Page 84 CHAPTER 5 CPU ARCHITECTURE Figure 5-2. Memory Map ( µ PD780054, 780054Y) FFFFH Special Function Registers (SFRs) 256 × 8 bits FF00H FEFFH General Registers 32 × 8 bits FEE0H FEDFH Internal High-speed RAM 1,024 × 8 bits FB00H FAFFH Unusable FAE0H 7FFFH...
Page 85 CHAPTER 5 CPU ARCHITECTURE Figure 5-3. Memory Map ( µ PD780055, 780055Y) FFFFH Special Function Registers (SFRs) 256 × 8 bits FF00H FEFFH General Registers 32 × 8 bits FEE0H FEDFH Internal High-speed RAM 1,024 × 8 bits FB00H FAFFH Unusable FAE0H 9FFFH...
Page 86 CHAPTER 5 CPU ARCHITECTURE Figure 5-4. Memory Map ( µ PD780056, 780056Y) FFFFH Special Function Registers (SFRs) 256 × 8 bits FF00H FEFFH General Registers 32 × 8 bits FEE0H FEDFH Internal High-speed RAM 1,024 × 8 bits FB00H FAFFH Unusable FAE0H BFFFH...
Page 87 CHAPTER 5 CPU ARCHITECTURE Figure 5-5. Memory Map ( µ PD780058, 780058Y) FFFFH Special Function Registers (SFRs) 256 × 8 bits FF00H FEFFH General Registers 32 × 8 bits FEE0H FEDFH Internal High-speed RAM 1,024 × 8 bits FB00H FAFFH Unusable FAE0H EFFFH...
Page 88 CHAPTER 5 CPU ARCHITECTURE Figure 5-6. Memory Map ( µ PD78F0058, 78F0058Y) FFFFH Special Function Registers (SFRs) 256 × 8 bits FF00H FEFFH General Registers 32 × 8 bits FEE0H FEDFH Internal High-speed RAM 1,024 × 8 bits FB00H FAFFH Unusable FAE0H EFFFH...
Page 89: Internal Program Memory Space
CHAPTER 5 CPU ARCHITECTURE 5.1.1 Internal program memory space The µ PD780058 and 780058Y Subseries have various sizes of internal ROM or flash memory as shown below. The internal program memory space stores programs and table data. Normally, they are addressed with a program counter (PC).
Page 90 CHAPTER 5 CPU ARCHITECTURE (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.
Page 91: Internal Data Memory Space
CHAPTER 5 CPU ARCHITECTURE 5.1.2 Internal data memory space The µ PD780058 and 780058Y Subseries incorporate the following RAMs. (1) Internal high-speed RAM High-speed memory of the following configuration is incorporated: 1,024 × 8 bits (FB00H to FEFFH) In this area, four banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH.
Page 92 CHAPTER 5 CPU ARCHITECTURE Figure 5-7. Data Memory Addressing ( µ PD780053, 780053Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH Internal High-speed RAM 1,024 ×...
Page 93 CHAPTER 5 CPU ARCHITECTURE Figure 5-8. Data Memory Addressing ( µ PD780054, 780054Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH Internal High-speed RAM 1,024 ×...
Page 94 CHAPTER 5 CPU ARCHITECTURE Figure 5-9. Data Memory Addressing ( µ PD780055, 780055Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH Internal High-speed RAM 1,024 ×...
Page 95 CHAPTER 5 CPU ARCHITECTURE Figure 5-10. Data Memory Addressing ( µ PD780056, 780056Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH Internal High-speed RAM 1,024 ×...
Page 96 CHAPTER 5 CPU ARCHITECTURE Figure 5-11. Data Memory Addressing ( µ PD780058, 780058Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH Internal High-speed RAM 1,024 ×...
Page 97 CHAPTER 5 CPU ARCHITECTURE Figure 5-12. Data Memory Addressing ( µ PD78F0058, 78F0058Y) FFFFH Special Function Registers (SFRs) SFR Addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH General Registers Register Addressing 32 × 8 bits Short Direct FEE0H Addressing FEDFH Internal High-speed RAM 1,024 ×...
Page 98: Processor Registers
CHAPTER 5 CPU ARCHITECTURE 5.2 Processor Registers The µ PD780058 and 780058Y Subseries incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 99 CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When IE = 0, all interrupt requests except the non-maskable interrupt are disabled (DI status). When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specify flag.
Page 100 CHAPTER 5 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FB00H to FEFFH) can be set as the stack area. Figure 5-15. Stack Pointer Format SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.
Page 101: General Registers
CHAPTER 5 CPU ARCHITECTURE 5.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register.
Page 102: Special Function Register (Sfr)
CHAPTER 5 CPU ARCHITECTURE 5.2.3 Special Function Register (SFR) Unlike a general register, each special-function register has special functions. It is allocated in the FF00H to FFFFH area. The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions.
Page 103 CHAPTER 5 CPU ARCHITECTURE Table 5-2. Special-Function Register List (1/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 1 bit 8 bits 16 bits √ √ FF00H Port0 — √ √ FF01H Port1 — √ √ FF02H Port2 —...
Page 104 CHAPTER 5 CPU ARCHITECTURE Table 5-2. Special-Function Register List (2/3) Manipulatable Bit Unit Address Special-Function Register (SFR) Name Symbol After Reset 8 bits 16 bits 1 bit √ Note FF38H Correction address register 0 CORAD0 — — 0000H FF39H √ Note FF3AH Correction address register 1...
Page 105 CHAPTER 5 CPU ARCHITECTURE Table 5-2. Special-Function Register List (3/3) Address Special-Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 bit 8 bits 16 bits √ √ Note 1 FFD0H to External access area — Undefined FFDFH IF0L √...
Page 106: Instruction Address Addressing
CHAPTER 5 CPU ARCHITECTURE 5.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The contents of PC are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 107: Immediate Addressing
CHAPTER 5 CPU ARCHITECTURE 5.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space.
Page 108 CHAPTER 5 CPU ARCHITECTURE 5.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Before the CALLT [addr5] instruction is executed, table indirect addressing is performed.
Page 109: Register Addressing
CHAPTER 5 CPU ARCHITECTURE 5.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]...
Page 110: Operand Address Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (illicitly) addressed.
Page 111: Register Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 112: Direct Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code...
Page 113: Short Direct Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An internal RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 114 CHAPTER 5 CPU ARCHITECTURE [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) 0 1 0 1 0 0 0 0 50H (immediate data) [Illustration]...
Page 115: Special-Function Register (Sfr) Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.5 Special-Function Register (SFR) addressing [Function] The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 116: Register Indirect Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.6 Register indirect addressing [Function] This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code.
Page 117: Based Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags (RBS0 and RBS1).
Page 118: Based Indexed Addressing
CHAPTER 5 CPU ARCHITECTURE 5.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition. The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select flags (RBS0 and RBS1).
Page 119: Chapter 6 Port Functions
CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD780058 and 780058Y Subseries units incorporate two input ports and sixty-six input/output ports. Figure 6-1 shows the port type. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations.
Page 120 CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions ( µ PD780058 Subseries) (1/2) Pin Name Function Alternate Function Port 0 Input only INTP0/TI00 7-bit input/output port INTP1/TI01 Input/output mode can be specified bit-wise. INTP2 If used as an input port, an on-chip pull-up INTP3 resistor can be used by software.
Page 121 CHAPTER 6 PORT FUNCTIONS Table 6-1. Port Functions ( µ PD780058 Subseries) (2/2) Pin Name Function Alternate Function Port 6 N-ch open-drain input/output port. — 8-bit input/output port On-chip pull-up resistor can be specified by Input/output mode can be specified mask option.
Page 122 CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions ( µ PD780058Y Subseries) (1/2) Pin Name Function Alternate Function Port 0 Input only INTP0/TI00 7-bit input/output port INTP1/TI01 Input/output mode can be specified bit-wise. INTP2 If used as an input port, an on-chip pull-up INTP3 resistor can be used by software.
Page 123 CHAPTER 6 PORT FUNCTIONS Table 6-2. Port Functions ( µ PD780058Y Subseries) (2/2) Pin Name Function Alternate Function Port 6 N-ch open-drain input/output port. — 8-bit input/output port On-chip pull-up resistor can be specified by Input/output mode can be specified mask option.
Page 124: Port Configuration
CHAPTER 6 PORT FUNCTIONS 6.2 Port Configuration A port consists of the following hardware: Table 6-3. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0 to 3, 5 to 10, 12, 13) Pull-up resistor option register (PUOH, PUOL) Note Memory expansion mode register (MM) Key return mode register (KRM)
Page 125 CHAPTER 6 PORT FUNCTIONS Figure 6-2. P00 and P07 Block Diagram P00/INTP0/TI00, P07/XT1 RD : Port 0 read signal Figure 6-3. P01 to P05 Block Diagram PUO0 P-ch Selector PORT P01/INTP1/TI01. Output Latch P02/INTP2 (P01 to P05) P05/INTP5 PM01 to PM05 PUO : Pull-up resistor option register PM : Port mode register : Port 0 read signal...
Page 126: Port 1
CHAPTER 6 PORT FUNCTIONS 6.2.2 Port 1 Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit unit with a port mode register 1 (PM1). When pins P10 to P17 are used as an input port, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 127: Port 2 ( Μ Pd780058 Subseries)
CHAPTER 6 PORT FUNCTIONS 6.2.3 Port 2 ( µ PD780058 Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as an input port, an on-chip pull- up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 128 CHAPTER 6 PORT FUNCTIONS Figure 6-6. P22 and P27 Block Diagram PUO2 P-ch Selector PORT Output Latch P22/SCK1, (P22, P27) P27/SCK0 PM22, PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal...
Page 129: Port 2 ( Μ Pd780058Y Subseries)
CHAPTER 6 PORT FUNCTIONS 6.2.4 Port 2 ( µ PD780058Y Subseries) Port 2 is an 8-bit input/output port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P27 pins are used as an input port, an on-chip pull- up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 130 CHAPTER 6 PORT FUNCTIONS Figure 6-8. P22 and P27 Block Diagram PUO2 P-ch Selector PORT Output Latch P22/SCK1, (P22 and P27) P27/SCK0/SCL PM22, PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 2 read signal WR : Port 2 write signal...
Page 131: Port 3
CHAPTER 6 PORT FUNCTIONS 6.2.5 Port 3 Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as an input port, an on-chip pull- up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 132: Port 4
CHAPTER 6 PORT FUNCTIONS 6.2.6 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins are used as input ports, an on- chip pull-up resistor can be used to them in 8-bit units with pull-up resistor option register L (PUOL).
Page 133: Port 5
CHAPTER 6 PORT FUNCTIONS 6.2.7 Port 5 Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as an input port, an on-chip pull- up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Page 134: Port 6
CHAPTER 6 PORT FUNCTIONS 6.2.8 Port 6 Port 6 is an 8-bit input/output port with output latch. P60 to P67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (PM6). This port has functions related to pull-up resistors as shown below. These functions depending on whether the higher 4 bits or lower 4 bits of a port are used, and whether the mask ROM model or flash memory model is used.
Page 135 CHAPTER 6 PORT FUNCTIONS Figure 6-13. P60 to P63 Block Diagram Mask Option Resistor Mask ROM versions only. Flash memory versions have no Selector pull-up resistor. PORT Output Latch P60 to P63 (P60 to P63) PM60 to PM63 PM : Port mode register RD : Port 6 read signal WR : Port 6 write signal Figure 6-14.
Page 136: Port 7
CHAPTER 6 PORT FUNCTIONS 6.2.9 Port 7 This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL).
Page 137 CHAPTER 6 PORT FUNCTIONS Figure 6-16. P71 and P72 Block Diagram PUO7 P-ch Selector PORT Output Latch P71/SO2/TxD0, (P71 and P72) P72/SCK2/ASCK PM71, PM72 Alternate Function PUO : Pull-up resistor option register PM : Port mode register : Port 7 read signal WR : Port 7 write signal...
Page 138 CHAPTER 6 PORT FUNCTIONS 6.2.10 Port 12 This is an 8-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 12 (PM12). When pins P120 to P127 are used as an input port pin, an on-chip pull-up resistor can be used as an 8-bit unit by means of pull-up resistor option register H (PUOH).
Page 139: Port 13
CHAPTER 6 PORT FUNCTIONS 6.2.11 Port 13 This is a 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 13 (PM13). When pins P130 and P131 are used as an input port pin, an on-chip pull-up resistor can be used as a 2-bit unit by means of pull-up resistor option register H (PUOH).
Page 140: Port Function Control Registers
CHAPTER 6 PORT FUNCTIONS 6.3 Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13) • Pull-up resistor option register (PUOH, PUOL) • Memory expansion mode register (MM) •...
Page 141 CHAPTER 6 PORT FUNCTIONS Table 6-5. Port Mode Register and Output Latch Settings When Using Alternate Functions Pin Name Alternate functions PM×× P×× Name Input/Output INTP0 Input 1 (Fixed) None TI00 Input 1 (Fixed) None × INTP1 Input × TI01 Input ×...
Page 142 CHAPTER 6 PORT FUNCTIONS Figure 6-19. Port Mode Register Format After Reset Symbol Address PM05 PM04 PM03 PM02 PM01 FF20H FF21H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H...
Page 143 CHAPTER 6 PORT FUNCTIONS (2) Pull-up resistor option register (PUOH, PUOL) This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL.
Page 144 CHAPTER 6 PORT FUNCTIONS (3) Memory expansion mode register (MM) This register is used to set input/output of port 4. MM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 6-21. Memory Expansion Mode Register Format After Symbol Address...
Page 145 CHAPTER 6 PORT FUNCTIONS (4) Key return mode register (KRM) This register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H.
Page 146: Port Function Operations
CHAPTER 6 PORT FUNCTIONS 6.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 147: Selection Of Mask Option
CHAPTER 6 PORT FUNCTIONS 6.5 Selection of Mask Option The following mask option is provided in mask ROM version. The flash memory versions have no mask options. Table 6-6. Comparison Between Mask ROM Version and Flash Memory Version Pin Name Mask ROM Version Flash Memory Version Mask option for pins P60 to P63...
Page 148 [MEMO]...
Page 149: Chapter 7 Clock Generator
CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).
Page 150 CHAPTER 7 CLOCK GENERATOR Figure 7-1. Clock Generator Block Diagram XT1/P07 Watch Timer, Subsystem Clock Output Clock Oscillator Function Prescaler Clock to Main Peripheral System Hardware Prescaler Clock Scaler Oscillator Standby Wait CPU Clock Control Control Circuit Circuit To INTP0 Sampling Clock STOP MCC FRC CLS CSS PCC2 PCC1...
Page 151: Clock Generator Control Register
CHAPTER 7 CLOCK GENERATOR 7.3 Clock Generator Control Register The clock generator is controlled by the following two registers: • Processor clock control register (PCC) • Oscillation mode selection register (OSMS) (1) Processor clock control register (PCC) PCC sets whether to use CPU clock selection, the ratio of division, main system clock oscillator operation/ stop and subsystem clock oscillator internal feedback resistor.
Page 152 CHAPTER 7 CLOCK GENERATOR Figure 7-3. Processor Clock Control Register Format After Symbol Address Reset Note 1 PCC2 PCC1 PCC0 FFFBH CPU CIock Selection (f PCC2 PCC1 PCC0 MCS = 1 MCS = 0 Other than above Setting prohibited CPU Clock Status Main system clock Subsystem clock Subsystem Clock Feedback Resistor Selection...
Page 153 CHAPTER 7 CLOCK GENERATOR The fastest instruction of the µ PD780058, 780058Y Subseries is executed in 2 CPU clocks. Therefore, the relation between the CPU clock (f ) and minimum instruction execution time is as shown in Table 7-2. Table 7-2. Relationships Between CPU Clock and Minimum Instruction Execution Time CPU Clock (f Minimum Instruction Execution Time: 2/f...
Page 154 CHAPTER 7 CLOCK GENERATOR (2) Oscillation mode selection register (OSMS) This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock.
Page 155: System Clock Oscillator
CHAPTER 7 CLOCK GENERATOR 7.4 System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin.
Page 156: Subsystem Clock Oscillator
CHAPTER 7 CLOCK GENERATOR 7.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin.
Page 157 CHAPTER 7 CLOCK GENERATOR Figure 7-8. Examples of Oscillator with Bad Connection (2/2) (c) Changing high current is too near a (d) Current flows through the grounding line signal conductor of the oscillator (potential at points A, B, and C fluctuate) High Current High Current...
Page 158: Divider
CHAPTER 7 CLOCK GENERATOR 7.4.3 Divider The divider divides the main system clock oscillator output (f ) and generates various clocks. 7.4.4 When not using subsystem clocks If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows.
Page 159: Clock Generator Operations
CHAPTER 7 CLOCK GENERATOR 7.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register (PCC) and the oscillation mode selection register (OSMS).
Page 160: Main System Clock Operations
CHAPTER 7 CLOCK GENERATOR 7.5.1 Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of the PCC.
Page 161: Subsystem Clock Operations
CHAPTER 7 CLOCK GENERATOR Figure 7-9. Main System Clock Stop Function (2/2) (c) Operation when CSS is set after setting MCC with main system clock operation Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock 7.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out.
Page 162: Changing System Clock And Cpu Clock Settings
CHAPTER 7 CLOCK GENERATOR 7.6 Changing System Clock and CPU Clock Settings 7.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC).
Page 163 Table 7-3. Maximum Time Required for CPU Clock Switchover Set Values before Set Values After Switchover Switchover MCS = 1 MCS = 0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1...
Page 164: System Clock And Cpu Clock Switching Procedure
CHAPTER 7 CLOCK GENERATOR 7.6.2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-10. System Clock and CPU Clock Switching RESET Interrupt Request Signal System Clock CPU Clock Minimum Maximum Speed Subsystem Clock High-Speed...
Page 165: Chapter 8 16-Bit Timer/Event Counter
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of Internal Timer of µ PD780058 and 780058Y Subseries This chapter explains the 16-bit timer/event counter. Before that, the timers incorporated into the µ PD780058 and 780058Y Subseries and the related functions are outlined below. (1) 16-bit timer/event counter (TM0) The TM0 can be used for an interval timer, PWM output, pulse widths measurement (infrared ray remote control receive function), external event counter, square wave output of any frequency or one-shot pulse output.
Page 166 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Operation 16-bit Timer/ 8-bit Timer/Event Watch Timer Watchdog Timer Event Counter Counters 1 and 2 Note 3 Note 1 Note 2 Operating Interval timer 2 channels 2 channels 1 channel 1 channel Mode √...
Page 167: 16-Bit Timer/Event Counter Functions
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 16-Bit Timer/Event Counter Functions The 16-bit timer/event counter (TM0) has the following functions. • Interval timer • PWM output • Pulse width measurement • External event counter • Square-wave output • One-shot pulse output PWM output and pulse width measurement can be used at the same time.
Page 168: 16-Bit Timer/Event Counter Square-Wave Output Ranges
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-3. 16-bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Time Maximum Pulse Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 × TI00 input cycle ×...
Page 169: 16-Bit Timer/Event Counter Configuration
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 16-Bit Timer/Event Counter Configuration The 16-bit timer/event counter consists of the following hardware. Table 8-4. 16-bit Timer/Event Counter Configuration Item Configuration 16 bits × 1 (TM0) Timer register Capture/compare register: 16 bits × 2 (CR00, CR01) Register Timer output 1 (TO0)
Page 170 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-1. 16-bit Timer/Event Counter Block Diagram Internal Bus Capture/Compare Control Register 0 CRC02 CRC01 CRC00 INTP1 16-Bit Capture/Compare TI01/ INTTM00 Control Register (CR00) P01/INTP1 PWM Pulse Match Output Note 2 INTTM3 Controller 16-Bit Timer/Event TO0/P30 Counter Output TMC01 to TMC03...
Page 171 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. 16-bit Timer/Event Counter Output Control Circuit Block Diagram PWM Pulse Level Output Control Inversion Circuit CRC02 INTTM01 CRC00 INTTM00 TO0/P30 Edge TI00/P00/ Detection One-Shot Pulse INTP0 Circuit Output Control Circuit P30 Output PM30 ES11 ES10 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0...
Page 172 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) Capture/compare register 00 (CR00) CR00 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register 0.
Page 173: 16-Bit Timer/Event Counter Control Registers
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer register (TM0) TM0 is a 16-bit register which counts the count pulses. TM0 is read by a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register (CR01) should first be set as a capture register. RESET input clears TM0 to 0000H.
Page 174 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-3. Timer Clock Select Register 0 Format Address After Reset Symbol TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 MCS = 1 MCS = 0 (32.768 kHz) (5.0 MHz) (2.5 MHz)
Page 175 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Remarks 1. f : Main system clock frequency (f or f 2. f : Main system clock oscillation frequency 3. f : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5. TM0 : 16-bit timer register 6.
Page 176 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-4. 16-bit Timer Mode Control Register Format Address After Reset Symbol TMC03 TMC02 TMC01 OVF0 TMC0 FF48H OVF0 16-Bit Timer Register Overflow Detection Overflow not detected Overflow detected Operating Mode or Interrupt Request TMC03 TMC02 TMC01 TO0 Output Timing Selection Clear Mode Selection Generation...
Page 177 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare control register 0 (CRC0) This register controls the operation of the capture/compare registers 00, 01 (CR00, CR01). CRC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 to 04H. Figure 8-5.
Page 178 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flip-flop (LV0) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation enabling/disabling, and output trigger for a one-shot pulse by software.
Page 179 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-6. 16-bit Timer Output Control Register Format Address After Reset Symbol TOC0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 FF4EH TOE0 16-Bit Timer/Event Counter Output Control Output disabled (Port mode) Output enabled In PWM Mode In Other Modes TOC01 Timer output F/F control...
Page 180 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Page 181 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) External interrupt mode register 0 (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 8-8. External Interrupt Mode Register 0 Format Address After Reset Symbol...
Page 182 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Sampling clock select registers (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed with sampling clock. SCS is set with an 8-bit memory manipulation instruction.
Page 183: 16-Bit Timer/Event Counter Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.
Page 184 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Interval Timer Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM00 INTTM3 OVF0 16-Bit Timer Register (TM0) TI00/P00/INTP0 Clear Circuit Figure 8-12. Interval Timer Operation Timings Count Clock TM0 Count Value 0000 0001 0000 0001 0000 0001 Count Start Clear...
Page 185: Pwm Output Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-6. 16-bit Timer/Event Counter Interval Times TCL06 TCL05 TCL04 Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 2 ×...
Page 186 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-13. Control Register Settings for PWM Output Operation (a) 16-bit timer mode control register (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 PWM mode (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00 CRC0 CR00 is set as compare register (c) 16-bit timer output control register (TOC0) OSPT OSPE...
Page 187 CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V ) used for D/A conversion with the configuration shown in Figure 8-14 is as follows. capture/compare register 00 (CR00) value ×...
Page 188: Ppg Output Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 PPG output operations Setting the 16-bit timer mode control register (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-16 allows operation as PPG (Programmable Pulse Generator) output. In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/ compare register 00 (CR00), respectively.
Page 189: Pulse Width Measurement Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.
Page 190 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. Configuration Diagram for Pulse Width Measurement by Free-Running Counter INTTM3 16-Bit Timer Register (TM0) OVF0 16-Bit Capture/Compare TI00/P00/INTP00 Register 01 (CR01) INTP0 Internal Bus Figure 8-19. Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) Count Clock TM0 Count Value...
Page 191 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-20), it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 pin and the TI01/P01 pin.
Page 192 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-21. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) Count Clock TM0 Count Value 0000 0001 FFFF 0000 TI00 Pin Input CR01 Captured Value INTP0 TI01 Pin Input CR00 Captured Value INTP1 OVF0 (10000H –...
Page 193 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When the 16-bit timer register (TM0) is operated in free-running mode (see register settings in Figure 8-22), it is possible to measure the pulse width of the signal input to the TI00/P00 pin. When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0) is set.
Page 194 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count Clock TM0 Count Value 0000 0001 FFFF 0000 TI00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 (D1 - D0) ×...
Page 195 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by means of restart When input of a valid edge to the TI00/P00 pin is detected, the count value of the 16-bit timer register (TM0) is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 8-24).
Page 196: External Event Counter Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00/P00 pin with the 16-bit timer register (TM0). TM0 is incremented each time the valid edge specified with the external interrupt mode register 0 (INTM0) is input. When the TM0 counted value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and the interrupt request signal (INTTM00) is generated.
Page 197 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. External Event Counter Configuration Diagram 16-Bit Capture/Compare Register 00 (CR00) INTTM00 Clear OVF0 16-Bit Timer Register (TM0) TI00 Valid Edge INTP0 16-Bit Capture/Compare Register 01 (CR01) Internal Bus Figure 8-28. External Event Counter Operation Timings (with Rising Edge Specified) TI00 Pin Input TM0 Count Value 0000 0001 0002 0003 0004 0005...
Page 198: Square-Wave Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.6 Square-wave output operation The 16-bit timer/event counter outputs a square wave with any selected frequency at intervals specified by the count value set in advance to the 16-bit capture/compare register 00 (CR00). The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0) and bit 1 (TOC01) of the 16-bit timer output control register (TOC0) to 1.
Page 199: 16-Bit Timer/Event Counter Square-Wave Output Ranges
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-30. Square-Wave Output Operation Timing Count Clock TM0 Count Value 0000 0001 0002 N - 1 0000 0001 0002 N - 1 0000 CR00 INTTM0 TO0 Pin Output Table 8-7. 16-bit Timer/Event Counter Square-Wave Output Ranges Minimum Pulse Time Maximum Pulse Time Resolution...
Page 200: One-Shot Pulse Output Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.7 One-shot pulse output operation It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin input). (1) One-shot pulse output using software trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-31, and 1 is set in bit 6 (OSPT) of TOC0 by software, a one-shot pulse is output from the TO0/P30 pin.
Page 201 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-32. One-Shot Pulse Output Operation Timing Using Software Trigger Set 0CH to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0001 N + 1 N - 1 M - 1 0000 0001 0002 0000 CR01 Set Value CR00 Set Value...
Page 202 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output using external trigger If the 16-bit timer mode control register (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer output control register (TOC0) are set as shown in Figure 8-33, a one-shot pulse is output from the TO0/ P30 pin with a TI00/P00 valid edge as an external trigger.
Page 203 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-34. One-Shot Pulse Output Operation Timing Using External Trigger (with Rising Edge Specified) Set 08H to TMC0 (TM0 count start) Count Clock TM0 Count Value 0000 0000 0001 N + 1 N + 2 M –...
Page 204: 16-Bit Timer/Event Counter Operating Cautions
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Cautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because the 16-bit timer register (TM0) is started asynchronously with the count pulse.
Page 205 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI00/P00 pin is input during 16-bit capture/compare register 01 (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag (PIF0) is set upon detection of the valid edge.
Page 206 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Operation of OVF0 flag OFV0 flag is set to 1 in the following case. The clear & start mode on match between TM0 and CR00 is selected. ↓ CR00 is set to FFFFH. ↓ When TM0 is counted up from FFFFH to 0000H.
Page 207: Chapter 9 8-Bit Timer/Event Counter
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.1 8-Bit Timer/Event Counter Functions For the 8-bit timer/event counter, two modes are available. One is a mode for two-channel 8-bit timer/event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode).
Page 208: 8-Bit Timer/Event Counters 1 And 2 Interval Times
CHAPTER 9 8-BIT TIMER/EVENT COUNTER (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-bit Timer/Event Counters 1 and 2 Interval Times Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1...
Page 209: 8-Bit Timer/Event Counters 1 And 2 Square-Wave Output Ranges
CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-2. 8-bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges Minimum Pulse Time Maximum Pulse Time Resolution...
Page 210: 16-Bit Timer/Event Counter Mode
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer Interrupt requests can be generated at the preset time intervals. Table 9-3. Interval Times When 8-bit Timer/Event Counters 1 and 2 Are Used as 16-bit Timer/Event Counters Minimum Interval Time Maximum Interval Time Resolution...
Page 211: Counters 1 And 2 Are Used As 16-Bit Timer/Event Counters
CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) External event counter The number of pulses of an externally input signal can be measured. (3) Square-wave output A square wave with any selected frequency can be output. Table 9-4. Square-Wave Output Ranges When 8-bit Timer/Event Counters 1 and 2 Are Used as 16-bit Timer/Event Counters Minimum Pulse Time Maximum Pulse Time...
Page 212: 8-Bit Timer/Event Counter Configurations
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.2 8-Bit Timer/Event Counter Configurations The 8-bit timer/event counter consists of the following hardware. Table 9-5. 8-bit Timer/Event Counter Configurations Item Configuration 8 bits × 2 (TM1, TM2) Timer register Compare register: 8 bits × 2 (CR10, CR20) Register Timer output 2 (TO1, TO2)
Page 213 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-1. 8-bit Timer/Event Counter Block Diagram Internal Bus INTTM1 8-Bit Compare 8-Bit Compare Register (CR20) Register 10 (CR10) Note 8-Bit Timer/ Match Event Counter TO2/P32 Output Control Match Circuit 2 /2 to f 8-Bit Timer Register 1 (TM1) 8-Bit Timer TI1/P33...
Page 214 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-2. Block Diagram of 8-bit Timer/Event Counter Output Control Circuit 1 Level F/F (LV1) LVR1 TO1/P31 LVS1 Note PM31 TOC11 Output Latch INTTM1 TOE1 Note Bit 1 of port mode register 3 (PM3) Remark The section in the broken line is an output control circuit. Figure 9-3.
Page 215 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (1) Compare registers 10 and 20 (CR10, CR20) These are 8-bit registers to compare the value set to CR10 to the 8-bit timer register 1 (TM1) count value, and the value set to CR20 to the 8-bit timer register 2 (TM2) count value, and, if they match, generate an interrupt request (INTTM1 and INTTM2, respectively).
Page 216: 8-Bit Timer/Event Counter Control Registers
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.3 8-Bit Timer/Event Counter Control Registers The following four types of registers are used to control the 8-bit timer/event counter. • Timer clock select register 1 (TCL1) • 8-bit timer mode control register 1 (TMC1) •...
Page 217 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-4. Timer Clock Select Register 1 Format Address After Reset Symbol TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10 FF41H 8-Bit Timer Register 1 Count Clock Selection TCL13 TCL12 TCL11 TCL10 MCS = 1 MCS = 0 TI1 falling edge TI1 rising edge...
Page 218 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) 8-bit timer mode control register (TMC1) This register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 1 and 2. TMC1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC1 to 00H.
Page 219 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (3) 8-bit timer output control register (TOC1) This register controls operation of 8-bit timer/event counter output control circuits 1 and 2. It sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of 8-bit timer registers 1 and 2.
Page 220 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (4) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and output latches of P31 and P32 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 221: 8-Bit Timer/Event Counters 1 And 2 Operations
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4 8-Bit Timer/Event Counters 1 and 2 Operations 9.4.1 8-bit timer/event counter mode (1) Interval timer operations The 8-bit timer/event counters 1 and 2 operate as interval timers that generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20). When the count values of the 8-bit timer registers 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated.
Page 222: 8-Bit Timer/Event Counter 1 Interval Time
CHAPTER 9 8-BIT TIMER/EVENT COUNTER Table 9-6. 8-bit Timer/Event Counter 1 Interval Time TCL13 TCL12 TCL11 TCL10 Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 ×...
Page 223 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Table 9-7. 8-bit Timer/Event Counter 2 Interval Time TCL17 TCL16 TCL15 TCL14 Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0 ×...
Page 224 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) External event counter operation The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/ P34 pins with 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register (TCL1) is input.
Page 225: 8-Bit Timer/Event Counters 1 And 2 Square-Wave Output Ranges
CHAPTER 9 8-BIT TIMER/EVENT COUNTER (3) Square-wave output operation The 8-bit timer/event counters 1 and 2 output a square wave with any selected frequency at intervals specified by the value set in advance to 8-bit compare registers 10 and 20 (CR10 and CR20). The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20 by setting bit 0 (TOE1) or bit 4 (TOE2) of the 8-bit timer output control register (TOC1) to 1.
Page 226 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-10. Square Wave Output Operation Timing Count Clock TM1 Count Value N – 1 N – 1 Count Start CR10 Note Note The initial value of the TO1 output can be set by bits 2 and 3 (LVS1 and LVR1) of the 8-bit timer output control register (TOC1).
Page 227: 16-Bit Timer/Event Counter Mode
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.4.2 16-bit timer/event counter mode When bit 2 (TMC12) of the 8-bit timer mode control register (TMC1) is set to 1, the 16-bit timer/event counter mode is set. In this mode, the count clock is selected by using bits 0 through 3 (TCL10 through TCL13) of the timer clock select register (TCL1), and the overflow signal of the 8-bit timer/event counter 1 (TM1) is used as the count clock for the 8-bit timer/event counter 2 (TM2).
Page 228 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Table 9-9. Interval Times When 2-channel 8-bit Timer/Event Counters (TM1 and TM2) Are Used as 16-bit Timer/Event Counter TCL13 TCL12 TCL11 TCL10 Minimum Interval Time Maximum Interval Time Resolution MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1...
Page 229 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (2) External event counter operations The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin with 2- channel 8-bit timer registers 1 and 2 (TM1 and TM2). TM1 is incremented each time the valid edge specified with the timer clock select register 1 (TCL1) is input.
Page 230 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (3) Square-wave output operation The 8-bit timer/event counters 1 and 2 output a square wave with any selected frequency at intervals specified by the value set in advance to 8-bit compare registers 10 and 20 (CR10 and CR20). To set a count value, set the value of the high-order 8 bits to CR20, and the value of the low-order 8 bits to CR10.
Page 231 CHAPTER 9 8-BIT TIMER/EVENT COUNTER Figure 9-13. Square Wave Output Operation Timing Count Clock M – 1 CR10 CR20 Interval Time Count Start Level Inversion Counter Clear...
Page 232: 8-Bit Timer/Event Counters 1 And 2 Precautions
CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.5 8-Bit Timer/Event Counters 1 and 2 Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because 8-bit timer registers 1 and 2 (TM1 and TM2) are started asynchronously with the count pulse.
Page 233 CHAPTER 9 8-BIT TIMER/EVENT COUNTER (3) Operation after compare register change during timer count operation If the values after the 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those of 8-bit timer registers (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart counting from 0.
Page 234 [MEMO]...
Page 235: Chapter 10 Watch Timer
CHAPTER 10 WATCH TIMER 10.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. (1) Watch timer When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals. When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5 second or 0.25 second intervals.
Page 236: Watch Timer Configuration
CHAPTER 10 WATCH TIMER 10.2 Watch Timer Configuration The watch timer consists of the following hardware. Table 10-2. Watch Timer Configuration Item Configuration 5 bits × 1 Counter Control register Timer clock select register 2 (TCL2) Watch timer mode control register (TMC2) 10.3 Watch Timer Control Registers The following two types of registers are used to control the watch timer.
Page 237 CHAPTER 10 WATCH TIMER Figure 10-1. Watch Timer Block Diagram TMC21 Clear 5-Bit Counter Prescaler INTWT Clear INTTM3 To 16-Bit Timer/ Event Counter TCL24 TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Watch Timer Mode Timer Clock Control Register Select Register 2 Internal Bus...
Page 238 CHAPTER 10 WATCH TIMER Figure 10-2. Timer Clock Select Register 2 Format After Address Symbol Reset TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H TCL2 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS = 1 MCS = 0 (625 kHz) (313 kHz) (313 kHz) (156 kHz)
Page 239 CHAPTER 10 WATCH TIMER (2) Watch timer mode control register (TMC2) This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/ disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears TMC2 to 00H.
Page 240: Watch Timer Operations
CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation When the 32.768-kHz subsystem clock or 4.19-MHz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. The watch timer sets the test input flag (WTIF) to 1 at the constant time interval. The standby state (STOP mode/ HALT mode) can be cleared by setting WTIF to 1.
Page 241: Chapter 11 Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (WDTM) (The watchdog timer and interval timer cannot be used at the same time). (1) Watchdog timer mode An inadvertent program loop (program runaway) is detected.
Page 242 CHAPTER 11 WATCHDOG TIMER (2) Interval timer mode Interrupt requests are generated at the preset time intervals. Table 11-2. Interval Times Interval Time MCS = 1 MCS = 0 × 1/f × 1/f (410 µ s) × 1/f (819 µ s) (819 µ...
Page 243: Watchdog Timer Configuration
CHAPTER 11 WATCHDOG TIMER 11.2 Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Watchdog Timer Configuration Item Configuration Control register Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 11-1. Watchdog Timer Block Diagram Internal Bus Prescaler TMMK4...
Page 244: Watchdog Timer Control Registers
CHAPTER 11 WATCHDOG TIMER 11.3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock select register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock.
Page 245 CHAPTER 11 WATCHDOG TIMER Figure 11-2. Timer Clock Select Register 2 Format After Address Symbol Reset TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H TCL2 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS = 1 MCS = 0 (625 kHz) (313 kHz) (313 kHz) (156 kHz)
Page 246 CHAPTER 11 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables/disables counting. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 11-3. Watchdog Timer Mode Register Format After Address Symbol...
Page 247: Watchdog Timer Operations
CHAPTER 11 WATCHDOG TIMER 11.4 Watchdog Timer Operations 11.4.1 Watchdog timer operation When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop. The watchdog timer count clock (program runaway detection time interval) can be selected with bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).
Page 248: Interval Timer Operation
CHAPTER 11 WATCHDOG TIMER 11.4.2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0. A count clock (interval time) can be selected by the bits 0 to 2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).
Page 249: Chapter 12 Clock Output Control Circuit
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/ P35 pin.
Page 250: Clock Output Control Circuit Configuration
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT 12.2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware. Table 12-1. Clock Output Control Circuit Configuration Item Configuration Control register Timer clock select register 0 (TCL0) Port mode register 3 (PM3) Figure 12-2.
Page 251 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Figure 12-3. Timer Clock Select Register 0 Format After Address Symbol Reset CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H TCL0 PCL Output Clock Selection TCL03 TCL02 TCL01 TCL00 MCS = 1 MCS = 0 (32.768 kHz) (5.0 MHz) /2 (2.5 MHz)
Page 252 CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT Remarks 1. f : Main system clock frequency (f or f 2. f : Main system clock oscillation frequency 3. f : Subsystem clock oscillation frequency 4. TI00 : 16-bit timer/event counter input pin 5.
Page 253: Chapter 13 Buzzer Output Control Circuit
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.1 Buzzer Output Control Circuit Functions The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin. Follow the procedure below to output the buzzer frequency.
Page 254: Buzzer Output Function Control Registers
CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT 13.3 Buzzer Output Function Control Registers The following two types of registers are used to control the buzzer output function. • Timer clock select register 2 (TCL2) • Port mode register 3 (PM3) (1) Timer clock select register 2 (TCL2) This register sets the buzzer output frequency.
Page 255 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT Figure 13-2. Timer Clock Select Register 2 Format After Address Symbol Reset TCL27 TCL26 TCL25 TCL24 TCL22 TCL21 TCL20 FF42H TCL2 Watchdog Timer Count Clock Selection TCL22 TCL21 TCL20 MCS = 1 MCS = 0 (625 kHz) (313 kHz) (313 kHz)
Page 256 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0. PM3 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM3 to FFH.
Page 257: Chapter 14 A/D Converter
CHAPTER 14 A/D CONVERTER 14.1 A/D Converter Functions The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an 8-bit resolution. The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR).
Page 258 CHAPTER 14 A/D CONVERTER Figure 14-1. A/D Converter Block Diagram Internal Bus A/ D Converter Input Select Register ADIS3 ADIS2 ADIS1 ADIS0 Series Resistor String ANI0/P10 ANI1/P11 Sample & Hold Circuit ANI2/P12 Voltage Note 1 Note 2 REF0 Comparator ANI3/P13 (also functions as ANI4/P14 analog power)
Page 259 CHAPTER 14 A/D CONVERTER (1) Successive approximation register (SAR) This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB). When up to the least significant bit (LSB) is held (termination of A/D conversion), the SAR contents are transferred to the A/D conversion result register (ADCR).
Page 260 CHAPTER 14 A/D CONVERTER (7) AV REF0 This pin inputs the A/D converter reference voltage. It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AV REF0 and AV The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AV REF0 pin to AV level in standby mode.
Page 261: A/D Converter Control Registers
CHAPTER 14 A/D CONVERTER 14.3 A/D Converter Control Registers The following three types of registers are used to control the A/D converter. • A/D converter mode register (ADM) • A/D converter input select register (ADIS) • External interrupt mode register 1 (INTM1) (1) A/D converter mode register (ADM) This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and external trigger.
Page 262 CHAPTER 14 A/D CONVERTER Figure 14-2. A/D Converter Mode Register Format After Address Symbol Reset ADM3 ADM2 ADM1 HSC FF80H ADM3 ADM2 ADM1 Analog Input Channel Selection ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Note 1 A/D Conversion Time Selection = 5.0-MHz Operation = 4.19-MHz Operation MCS = 1...
Page 263 CHAPTER 14 A/D CONVERTER (2) A/D converter input select register (ADIS) This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports. ADIS is set with an 8-bit memory manipulation instruction.
Page 264 CHAPTER 14 A/D CONVERTER (3) External interrupt mode register 1 (INTM1) This register sets the valid edge for INTP3 to INTP5. INTM1 is set with an 8-bit memory manipulation instruction. RESET input clears INTM1 to 00H. Figure 14-4. External Interrupt Mode Register 1 Format After Address Symbol...
Page 265: A/D Converter Operations
CHAPTER 14 A/D CONVERTER 14.4 A/D Converter Operations 14.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with A/D converter input select register (ADIS). (2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM).
Page 266 CHAPTER 14 A/D CONVERTER Figure 14-5. A/D Converter Basic Operation Conversion Time Sampling Time A/D Converter Sampling A /D Conversion Operation Conversion Undefined Result Conversion ADCR Result INTAD A/D conversion operations are performed continuously until the bit 7 (CS) of AD converter mode register (ADM) is reset (to 0) by software.
Page 267: Input Voltage And Conversion Results
CHAPTER 14 A/D CONVERTER 14.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression. ×...
Page 268: A/D Converter Operating Mode
CHAPTER 14 A/D CONVERTER 14.4.3 A/D converter operating mode One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS) and A/D converter mode register (ADM) and A/D conversion is started. The following two ways are available to start A/D conversion. •...
Page 269 CHAPTER 14 A/D CONVERTER (2) A/D conversion operation in software start When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.
Page 270: A/D Converter Cautions
CHAPTER 14 A/D CONVERTER 14.5 A/D Converter Cautions (1) Power consumption in standby mode The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in HALT mode with the subsystem clock. As a current still flows in the AV pin at this time, this current must REF0 be cut in order to minimize the overall system power consumption.
Page 271 CHAPTER 14 A/D CONVERTER (3) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on AV and ANI0 to ANI7 pins. Since REF0 the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 14-10 in order to reduce noise.
Page 272 CHAPTER 14 A/D CONVERTER (6) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed. Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADM rewrite.
Page 273: Chapter 15 D/A Converter
CHAPTER 15 D/A CONVERTER 15.1 D/A Converter Functions The D/A converter converts a digital input into an analog value. It consists of two 8-bit resolution channels of voltage output type D/A converter. The conversion method used is the R-2R resistor ladder method. Start the D/A conversion by setting bits 0 and 1 (DACE0 and DACE1) of the D/A converter mode register (DAM).
Page 274: D/A Converter Configuration
CHAPTER 15 D/A CONVERTER 15.2 D/A Converter Configuration The D/A converter consists of the following hardware. Table 15-1. D/A Converter Configuration Item Configuration Register D/A conversion value set register 0 (DACS0) D/A conversion value set register 1 (DACS1) Control register D/A converter mode register (DAM) Figure 15-1.
Page 275 CHAPTER 15 D/A CONVERTER (1) D/A conversion value set register 0, 1 (DACS0, DACS1) DACS0 and DACS1 are registers that set the values used to determine the analog voltages to be output to the ANO0 and ANO1 pins, respectively. DACS0 and DACS1 are set with an 8-bit memory manipulation instruction. RESET input clears these registers to 00H.
Page 276: D/A Converter Control Registers
CHAPTER 15 D/A CONVERTER 15.3 D/A Converter Control Registers The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation enable/stop. The DAM is set with a 1-bit or an 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 15-2.
Page 277: D/A Converter Operations
CHAPTER 15 D/A CONVERTER 15.4 D/A Converter Operations (1) The channel 0 operating mode and channel 1 operating mode are selected by bits 4 and 5 (DAM4 and DAM5), respectively, of the D/A converter mode register (DAM). (2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins to the D/A conversion value setting registers 0 and 1 (DACS0 and DACS1), respectively.
Page 278: D/A Converter Cautions
CHAPTER 15 D/A CONVERTER 15.5 D/A Converter Cautions (1) Output impedance of D/A converter Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pins (n = 0,1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the ANOn pins.
Page 279: Chapter 16 Serial Interface Channel 0 ( Μ Pd780058 Subseries)
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) The µ PD780058 Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.
Page 280: Serial Interface Channel 0 Functions
This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1) (refer to Figure 16-1). The SBI mode conforms to the NEC serial bus format, and transmits or receives three types of transfer data: “addresses”, “commands”, “data”.
Page 281 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (4) 2-wire serial I/O mode (MSB-first) This mode is used for 8-bit data transfer using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level.
Page 282: Serial Interface Channel 0 Configuration
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) 16.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 16-2. Serial Interface Channel 0 Configuration Item Configuration Register Serial I/O shift register 0 (SIO0) Slave address register (SVA) Control register Timer clock select register 3 (TCL3)
Page 283 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) Figure 16-2. Serial Interface Channel 0 Block Diagram Internal Bus Serial Bus Interface Serial Operating Mode Register 0 Control Register Slave Address CSIM CSIM CSIM CSIM CSIM CSIE0 COI WUP BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Register (SVA) SVAM...
Page 284 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. The SIO0 is set with an 8-bit memory manipulation instruction.
Page 285 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (3) SO0 latch This latch holds SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In the SBI mode, this latch is set upon termination of the 8th serial clock. (4) Serial clock counter This counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received.
Page 286: Serial Interface Channel 0 Control Registers
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) 16.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...
Page 287 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) Figure 16-3. Timer Clock Select Register 3 Format Symbol Address After Reset TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 MCS = 1 MCS = 0 Setting prohibited...
Page 288 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or an 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
Page 289 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) Figure 16-4. Serial Operating Mode Register 0 Format (2/2) Wake-up Function Control Note 1 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode Slave Address Comparison Result Flag Note 2...
Page 290 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. Figure 16-5.
Page 291 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) Figure 16-5. Serial Bus Interface Control Register Format (2/2) ACKE Acknowledge Signal Automatic Output Control Acknowledge signal automatic output disable (output with ACKT enable) Acknowledge signal is output in synchronization with the falling edge of the 9th Before completion of transfer SCK0 clock (automatically output when ACKE = 1).
Page 292 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/P27 pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H.
Page 293: Serial Interface Channel 0 Operations
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) 16.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • SBI mode •...
Page 294: 3-Wire Serial I/O Mode Operation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) 16.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
Page 295 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) Symbol Address After Reset CSIM0 CSIE0 COI FF60H Note 1 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection CSIM01 CSIM00 × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) Operation...
Page 296 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. Symbol Address After Reset SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H RELT When RELT = 1, SO0 Iatch is set to 1.
Page 297 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
Page 298 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 16-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.
Page 299: Sbi Mode Operation
16.4.3 SBI mode operation SBI (Serial Bus Interface) is a high-speed serial interface in compliance with the NEC serial bus format. SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration function.
Page 300 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (1) SBI functions In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available.
Page 301 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (2) SBI definition The SBI serial data format and the signals to be used are defined as follows. Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”. Figure 16-11 shows the address, command, and data transfer timings.
Page 302 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (a) Bus release signal (REL) The bus release signal is a signal with the SB0 (SB1) line which has changed from the low level to the high level when the SCK0 line is at the high level (without serial clock output). This signal is output by the master device.
Page 303 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (c) Address An address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. Figure 16-14. Addresses SCK0 SB0 (SB1) Address...
Page 304 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (d) Command and data The master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. Figure 16-16. Commands SCK0 SB0 (SB1) Command Command Signal Figure 16-17.
Page 305 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (e) Acknowledge signal (ACK) The acknowledge signal is used to check serial data reception between transmitter and receiver. Figure 16-18. Acknowledge Signal [When output in synchronization with 11th clock SCK0] SCK0 SB0 (SB1) [When output in synchronization with 9th clock SCK0]...
Page 306 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (f) Busy signal (BUSY) and ready signal (READY) The BUSY signal is intended to report to the master device that the slave device is preparing for data transmission/reception. The READY signal is intended to report to the master device that the slave device is ready for data transmission/reception.
Page 307 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (3) Register setting The SBI mode is set with the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 308 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. The shaded area is used in the SBI mode. Symbol Address After Reset...
Page 309 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) ACKD Acknowledge Detection Clear Conditions (ACKD = 0) Set Conditions (ACKD = 1) • SCK0 fall immediately after the busy mode is • When acknowledge signal (ACK) is detected at the released during the transfer start instruction execution.
Page 310 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (c) Interrupt timing specify register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H. Symbol Address After Reset SINT SIC SVAM FF63H Note 1 SVAM...
Page 311 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (4) Various signals Figures 16-20 to 16-25 show various signals and flag operations in SBI. Table 16-3 lists various signals in SBI. Figure 16-20. RELT, CMDT, RELD, and CMDD Operations (Master) Slave address write to SIO0 (Transfer Start Instruction) SIO0...
Page 312 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) Figure 16-22. ACKT Operation SCK0 ACK signal is output for SB0 (SB1) a period of one clock just after setting ACKT If the ACKT is set during this period Caution Do not set ACKT before completion of transfer.
Page 313 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) Figure 16-23. ACKE Operations (a) When ACKE = 1 upon completion of transfer SCK0 ACK signal is output SB0 (SB1) at 9th clock ACKE When ACKE = 1 at this point (b) When set after completion of transfer SCK0 SB0 (SB1)
Page 314 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) Figure 16-24. ACKD Operations (a) When ACK signal is output at 9th SCK0 clock Transfer Start Instruction SIO0 Transfer Start SCK0 SB0 (SB1) ACKD (b) When ACK signal is output after 9th SCK0 clock Transfer Start Instruction SIO0...
Page 315 Table 16-3. Various Signals in SBI Mode (1/2) Output Output Signal Name Definition Timing Chart Effects on Flag Meaning of Signal Device Condition SB0 (SB1) rising edge Bus release Master • RELT set • RELD set CMD signal is output SCK0 "H"...
Page 316 Table 16-3. Various Signals in SBI Mode (2/2) Output Output Signal Name Definition Timing Chart Effects on Flag Meaning of Signal Condition Device When CSIE0 = 1, CSIIF0 set (rising Timing of signal Serial clock Master Synchronous clock to execution of edge of 9th clock output to serial data (SCK0)
Page 317 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (5) Pin configuration The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations. (a) SCK0 .... Serial clock input/output pin Master ... CMOS and push-pull output Slave ..
Page 318 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (6) Address match detection method In the SBI mode, the master transmits a slave address to select a specific slave device. Coincidence of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave address transmitted by the master coincides with the address set to SVA when the wake-up function specify bit (WUP) = 1.
Page 319 Figure 16-27. Address Transmission from Master Device to Slave Device (WUP = 1) Master Device Processing (Transmitter) Write Interrupt Servicing CMDT RELT CMDT Program Processing to SIO0 (Preparation for the Next Serial Transfer) INTCSI0 ACKD SCK0 Hardware Operation Serial Transmission Generation Stop Transfer Line...
Page 320 Figure 16-28. Command Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Write Interrupt Servicing CMDT Program Processing to SIO0 (Preparation for the Next Serial Transfer) INTCSI0 ACKD SCK0 Hardware Operation Serial Transmission Generation Stop Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY READY...
Page 321 Figure 16-29. Data Transmission from Master Device to Slave Device Master Device Processing (Transmitter) Write Interrupt Servicing Program Processing to SIO0 (Preparation for the Next Serial Transfer) INTCSI0 ACKD SCK0 Hardware Operation Serial Transmission Generation Stop Transfer Line SCK0 Pin SB0 (SB1) Pin BUSY READY...
Page 322 Figure 16-30. Data Transmission from Slave Device to Master Device Master Device Processing (Receiver) SIO0 FFH Write FFH Write ACKT Program Processing Receive data processing Read to SIO0 to SIO0 INTCSI0 Serial SCK0 Hardware Operation Serial Reception Reception Stop Generation Output Transfer Line SCK0 Pin...
Page 323 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (9) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied. • Serial interface channel 0 operation control bit (CSIE0) = 1 •...
Page 324 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (11) SBI mode precautions (a) Slave selection/non-selection is detected by match detection of the slave address received after bus release (RELD = 1). For this match detection, match interrupt request (INTCSI0) of the address to be generated with WUP = 1 is normally used.
Page 325: 2-Wire Serial I/O Mode Operation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) 16.4.4 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
Page 326 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) Symbol Address After Reset CSIM0 CSIE0 COI FF60H Note 1 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection CSIM01 CSIM00 × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM...
Page 327 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. Symbol Address After Reset SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H RELT When RELT = 1, SO0 Iatch is set to 1.
Page 328 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
Page 329 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) (3) Other signals Figure 16-33 shows RELT and CMDT operations. Figure 16-33. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
Page 330: Sck0/P27 Pin Output Manipulation
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( µ PD780058 Subseries) 16.4.5 SCK0/P27 pin output manipulation Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. P27 output latch manipulation enables any value of SCK0 to be set by software. (SI0/SB0 and SO0/SB1 pin to be controlled with the bits 0 and 1 (RELT and CMDT) of serial bus interface control register (SBIC).) SCK0/P27 pin output manipulating procedure is described below.
Page 331: Chapter 17 Serial Interface Channel 0 ( Μ Pd780058Y Subseries)
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) The µ PD780058Y Subseries incorporates three channels of serial interfaces. Differences between channels 0, 1, and 2 are as follows (Refer to CHAPTER 18 SERIAL INTERFACE CHANNEL 1 for details of the serial interface channel 1.
Page 332: Serial Interface Channel 0 Functions
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) 17.1 Serial Interface Channel 0 Functions Serial interface channel 0 employs the following four modes. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode • I C (Inter IC) bus mode Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial interface channel 0 is enabled to operate.
Page 333 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (4) I C (Inter IC) bus mode (MSB-first) This mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (SCL) and serial data bus (SDA0 or SDA1). This mode is in compliance with the I C bus format.
Page 334: Serial Interface Channel 0 Configuration
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) 17.2 Serial Interface Channel 0 Configuration Serial interface channel 0 consists of the following hardware. Table 17-2. Serial Interface Channel 0 Configuration Item Configuration Register Serial I/O shift register 0 (SIO0) Slave address register (SVA) Control register Timer clock select register 3 (TCL3)
Page 335 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-2. Serial Interface Channel 0 Block Diagram Internal Bus Serial Bus Interface Serial Operating Mode Register 0 Control Register Slave Address CSIM CSIM CSIM CSIM CSIM CSIE0 COI WUP BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Register (SVA) SVAM...
Page 336 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (1) Serial I/O shift register 0 (SIO0) This is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. SIO0 is set with an 8-bit memory manipulation instruction.
Page 337 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (6) Interrupt signal generator This circuit controls interrupt request signal generation. It generates interrupt request signals according to the settings of interrupt timing specification register (SINT) bits 0 and 1 (WAT0, WAT1) and serial operation mode register 0 (CSIM0) bit 5 (WUP), as shown in Table 17-3.
Page 338: Serial Interface Channel 0 Control Registers
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) 17.3 Serial Interface Channel 0 Control Registers The following four types of registers are used to control serial interface channel 0. • Timer clock select register 3 (TCL3) • Serial operating mode register 0 (CSIM0) •...
Page 339 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-3. Timer Clock Select Register 3 Format Symbol Address After Reset TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H Serial Interface Channel 0 Serial Clock Selection TCL33 TCL32 TCL31 TCL30 Serial Clock in 2-Wire or 3-Wire Serial Clock in I C Bus Mode...
Page 340 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (2) Serial operating mode register 0 (CSIM0) This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM0 to 00H.
Page 341 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (3) Serial bus interface control register (SBIC) This register sets serial bus interface operation and displays statuses. SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. Figure 17-5.
Page 342 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-5. Serial Bus Interface Control Register Format (2/2) Note 1 ACKE Acknowledge Signal Output Control Disables acknowledge signal automatic output. (However, output with ACKT is enabled) Note 2 Used for reception when 8-clock wait mode is selected or for transmission. Enables acknowledge signal automatic output.
Page 343 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (4) Interrupt timing specify register (SINT) This register sets the bus release interrupt and address mask functions and displays the SCK0/SCL pin level status. SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H.
Page 344 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-6. Interrupt Timing Specify Register Format (2/2) SVAM SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 INTCSI0 Interrupt Sourse Selection Note 1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer Note 2...
Page 345: Serial Interface Channel 0 Operations
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) 17.4 Serial Interface Channel 0 Operations The following four operating modes are available to the serial interface channel 0. • Operation stop mode • 3-wire serial I/O mode • 2-wire serial I/O mode •...
Page 346: 3-Wire Serial I/O Mode Operation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) 17.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series. Communication is carried out with three lines of serial clock (SCK0), serial output (SO0), and serial input (SI0).
Page 347 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. Symbol Address After Reset SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H When RELT = 1, SO0 Iatch is set to 1.
Page 348 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out at the falling edge of the serial clock (SCK0). The transmitted data is held in the SO0 latch and is output from the SO0 pin.
Page 349 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (4) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 17-9 shows the configuration of the serial I/O shift register 0 (SIO0) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.
Page 350: 2-Wire Serial I/O Mode Operation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) 17.4.3 2-wire serial I/O mode operation The 2-wire serial I/O mode can cope with any communication format by program. Communication is basically carried out with two lines of serial clock (SCK0) and serial data input/output (SB0 or SB1).
Page 351 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Symbol Address After Reset CSIM0 CSIE0 COI FF60H Note 1 CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 Serial Interface Channel 0 Clock Selection CSIM01 CSIM00 × Input clock to SCK0 pin from off-chip 8-bit timer register 2 (TM2) output Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3) CSIM...
Page 352 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. Symbol Address After Reset SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H RELT When RELT = 1, SO0 Iatch is set to 1.
Page 353 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (2) Communication operation The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception is carried out bit-wise in synchronization with the serial clock. Shift operation of the serial I/O shift register 0 (SIO0) is carried out in synchronization with the falling edge of the serial clock (SCK0).
Page 354 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (3) Other signals Figure 17-12 shows RELT and CMDT operations. Figure 17-12. RELT and CMDT Operations SO0 Latch RELT CMDT (4) Transfer start Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following two conditions are satisfied.
Page 355: I 2 C Bus Mode Operation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) 17.4.4 I C bus mode operation The I C bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. This mode configures a serial bus that includes only a single master device, and is based on the clocked serial I/O format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: serial clock (SCL) line and serial data bus (SDA0 or SDA1) line.
Page 356 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (1) I C bus mode functions In the I C bus mode, the following functions are available. (a) Automatic identification of serial data Slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus.
Page 357 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (a) Start condition When the SDA0 (SDA1) pin level is changed from high to low while the SCL pin is high, this transition is recognized as the start condition signal. This start condition signal, which is created using the SCL and SDA0 (or SDA1) pins, is output from the master device to slave devices to initiate a serial transfer.
Page 358 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (d) Acknowledge signal (ACK) The acknowledge signal indicates that the transferred serial data has definitely been received. This signal is used between the sending side and receiving side devices for confirmation of correct data transfer.
Page 359 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (f) Wait signal (WAIT) The wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. During the wait state, the slave device continues to output the wait signal by keeping the SCL pin low to delay subsequent transfers.
Page 360 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (3) Register setting The I C mode setting is performed by the serial operating mode register 0 (CSIM0), the serial bus interface control register (SBIC), and the interrupt timing specify register (SINT). (a) Serial operating mode register 0 (CSIM0) CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
Page 361 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (b) Serial bus interface control register (SBIC) SBIC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SBIC to 00H. Symbol Address After Reset Note 1 SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H...
Page 362 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (c) Interrupt timing specification register (SINT) SINT is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SINT to 00H. Symbol Address After Reset Note 1 SINT SVAM CLC WREL WAT1 WAT0 FF63H Note 2...
Page 363 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (4) Various signals A list of signals in the I C bus mode is given in Table 17-4. Table 17-4. Signals in I C Bus Mode Signal name Description Note 1 Start condition Definition : SDA0 (SDA1) falling edge when SCL is high...
Page 364 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (5) Pin configurations The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below. (a) SCL Pin for serial clock input/output alternate function pin. <1>...
Page 365 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (7) Error detection In the I C bus mode, transmission error detection can be performed by the following methods because the serial bus SDA0 (SDA1) status during transmission is also taken into the serial I/O shift register 0 (SIO0) register of the transmitting device.
Page 366 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-clock Wait) (1/3) (a) Start Condition to Address Master Device Operation SIO0 ← Address SIO0 ← Data Write SIO0 ACKD CMDD...
Page 367 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-clock Wait) (2/3) (b) Data Master Device Operation SIO0 ← Address SIO0 ← Data Write SIO0 ACKD CMDD RELD BSYE...
Page 368 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-22. Data Transmission from Master to Slave (Both Master and Slave Selected 9-clock Wait) (3/3) (c) Stop Condition Master Device Operation SIO0 ← Data SIO0 ← Address Write SIO0 ACKD CMDD RELD...
Page 369 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-clock Wait) (1/3) (a) Start Condition to Address Master Device Operation SIO0 ← FFH SIO0 ← Address Write SIO0 ACKD CMDD...
Page 370 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-clock Wait) (2/3) (b) Data Master Device Operation SIO0 ← FFH SIO0 ← FFH Write SIO0 ACKD CMDD RELD BSYE...
Page 371 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-23. Data Transmission from Slave to Master (Both Master and Slave Selected 9-clock Wait) (3/3) (c) Stop Condition Master Device Operation SIO0 ← FFH SIO0 ← Address Write SIO0 ACKD CMDD RELD...
Page 372: Bus Mode
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (9) Transfer start A serial transfer is started by setting transfer data in serial I/O shift register 0 (SIO0) if the following two conditions have been satisfied: • The serial interface channel 0 operation control bit (CSIE0) = 1. •...
Page 373 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (2) Slave wait release (slave transmission) Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting or execution of an serial I/O shift register 0 (SIO0) write instruction. If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line.
Page 374 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (3) Slave wait release (slave reception) The slave is released from the wait status when the WREL flag (bit 2 of the interrupt timing specify register (SINT)) is set or when an instruction that writes data to the serial I/O shift register 0 (SIO0) is executed. When the slave receives data, the first bit of the data sent from the master may not be received if the SCL line immediately goes into a high-impedance state after an instruction that writes data to SIO has been executed.
Page 375: Bus Mode
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) (4) Reception completion of salve In the reception completion processing of the slave, check the bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of the serial operation mode register 0 (CSIM0) (when CMDD = 1). This is to avoid the situation where the slave cannot judge which of the start condition and data comes first and therefore, the wake-up condition cannot be used when the slave receives the undefined number of data from the master.
Page 376 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) • Example of program releasing serial transfer status SET1 P2.5; <1> SET1 PM2.5; <2> SET1 PM2.7; <3> CLR1 CSIE0; <4> SET1 CSIE0; <5> SET1 RELT; <6> CLR1 PM2.7; <7> CLR1 P2.5;...
Page 377: Sck0/Scl/P27 Pin Output Manipulation
CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) 17.4.7 SCK0/SCL/P27 pin output manipulation The SCK0/SCL/P27 pin can execute static output via software, in addition to outputting the normal serial clock. The value of serial clocks can also be arbitrarily set by software (the SI0/SB0/SDA0 and SO0/SB1/SDA1 pins are controlled with the bit 0 (RELT) and bit 1 (CMDT) of serial bus interface control register (SBIC)).
Page 378 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( µ PD780058Y Subseries) Figure 17-29. Logic Circuit of SCL Signal CLC (manipulated by bit manipulation instruction) Wait request signal Serial clock (low while transfer is stopped) Remarks 1. This figure indicates the relation of the signals and does not indicate the internal circuit. 2.
Page 379: Chapter 18 Serial Interface Channel 1
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.1 Serial Interface Channel 1 Functions Serial interface channel 1 employs the following three modes. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.
Page 380: Serial Interface Channel 1 Configuration
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.2 Serial Interface Channel 1 Configuration Serial interface channel 1 consists of the following hardware. Table 18-1. Serial Interface Channel 1 Configuration Item Configuration Register Serial I/O shift register 1 (SIO1) Automatic data transmit/receive address pointer (ADTP) Control register Timer clock select register 3 (TCL3) Serial operating mode register 1 (CSIM1)
Page 381 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-1. Serial Interface Channel 1 Block Diagram Internal Bus Automatic Data Transmit/Receive Buffer RAM Address Pointer (ADTP) Internal Bus Automatic Data Automatic Data Transmit/Receive Interval Serial Operating Transmit/Receive Specify Register Mode Register 1 Control Register CSIE1 DIR ATE CSIM CSIM...
Page 382 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (1) Serial I/O shift register 1 (SIO1) This is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. The SIO1 is set with an 8-bit memory manipulation instruction. When the value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts serial operation.
Page 383: Serial Interface Channel 1 Control Registers
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.3 Serial Interface Channel 1 Control Registers The following four types of registers are used to control serial interface channel 1. • Timer clock select register 3 (TCL3) • Serial operating mode register 1 (CSIM1) •...
Page 384 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-2. Timer Clock Select Register 3 Format Symbol Address After Reset TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H Serial Interface Channel 1 Serial Clock Selection TCL37 TCL36 TCL35 TCL34 MCS = 1 MCS = 0 Setting prohibited (1.25 MHz)
Page 385 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Serial operating mode register 1 (CSIM1) This register sets serial interface channel 1 serial clock, operating mode, operation enable/stop and automatic transmit/receive operation enable/stop. CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM1 to 00H.
Page 386 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Automatic data transmit/receive control register (ADTC) This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error detection. ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADTC to 00H.
Page 387 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADTI to 00H. Figure 18-5.
Page 388 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (2/4) Symbol Address After Reset ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH Data Transfer Interval Specification (f = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Minimum Note...
Page 389 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (3/4) Symbol Address After Reset ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH ADTI7 Data Transfer Interval Control No control of interval by ADTI Note 1 Control of interval by ADTI (ADTI0 to ADTI4) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0...
Page 390 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-5. Automatic Data Transmit/Receive Interval Specify Register Format (4/4) Symbol Address After Reset ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Data Transfer Interval Specification (f = 2.5 MHz Operation) Minimum Note Maximum...
Page 391: Serial Interface Channel 1 Operations
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4 Serial Interface Channel 1 Operations The following three operating modes are available to the serial interface channel 1. • Operation stop mode • 3-wire serial I/O mode • 3-wire serial I/O mode with automatic transmit/receive function 18.4.1 Operation stop mode Serial transfer is not carried out in the operation stop mode.
Page 392: 3-Wire Serial I/O Mode Operation
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.2 3-wire serial I/O mode operation The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X/XL, 78K and 17K Series. Communication is carried out with three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1).
Page 393 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Communication operation The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Bit-wise data transmission/ reception is carried out in synchronization with the serial clock. Shift operation of the serial I/O shift register 1 (SIO1) is carried out at the falling edge of the serial clock SCK1. The transmit data is held in the SO1 latch and is output from the SO1 pin.
Page 394 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) MSB/LSB switching as the start bit The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB. Figure 18-7 shows the configuration of the serial I/O shift register 1 (SIO1) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.
Page 395: 3-Wire Serial I/O Mode Operation With Automatic Transmit/Receive Function
CHAPTER 18 SERIAL INTERFACE CHANNEL 1 18.4.3 3-wire serial I/O mode operation with automatic transmit/receive function This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32-byte data without the use of software. Once transfer is started, the data prestored in the RAM can be transmitted by the set number of bytes, and data can be received and stored in the RAM by the set number of bytes.
Page 396 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol Address After Reset CSIM1 CSIE1 DIR FF68H CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection CSIM11 CSIM10 × External clock input to SCK1 pin Note 1 8-bit timer register 2 (TM2) output Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3) Serial Interface Channel 1 Operating Mode Selection 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function...
Page 397 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Automatic data transmit/receive control register (ADTC) ADTC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADTC to 00H. Symbol Address After Reset ADTC ARLD ERCE ERR TRF STRB BUSY1 BUSY0 FF69H Note 1...
Page 398 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Automatic data transmit/receive interval specify register (ADTI) This register sets the automatic data transmit/receive function data transfer interval. ADTI is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADTI to 00H. Symbol Address After Reset...
Page 399 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol Address After Reset ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH Data Transfer Interval Specification (f = 5.0 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Minimum Maximum Note Note µ µ 223.2 s + 0.5/f 224.8 s + 1.5/f µ...
Page 400 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol Address After Reset ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH ADTI7 Data Transfer Interval Control No control of interval by ADT I Note 1 Control of interval by ADTI (ADTI0 to ADTI4) Data Transfer Interval Specification (f = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1...
Page 401 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Symbol Address After Reset ADTI ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH Data Transfer Interval Specification (f = 2.5 MHz Operation) ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 Minimum Note Maximum Note µ µ 446.4 s + 0.5/f 449.6 s + 1.5/f µ...
Page 402 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (2) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FAC0H of buffer RAM (up to FADFH at maximum). The transmit data should be in the order from high-order address to low-order address. <2>...
Page 403 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (3) Communication operation (a) Basic transmission/reception mode This transmission/reception mode is the same as the 3-wire serial I/O mode in which specified number of data are transmitted/received in 8-bit units. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1.
Page 404 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-9. Basic Transmission/Reception Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software Execution Set the transmission/reception operation interval time in ADTI Write any data to SIO1...
Page 405 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission/reception (ARLD = 0, RE = 1) in basic transmit/receive mode, internal buffer RAM operates as follows. (i) Before transmission/reception (see Figure 18-10 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1.
Page 406 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-10. Internal Buffer RAM Operation in 6-byte Transmission/Reception (in Basic Transmit/Receive Mode) (2/2) (b) 4th byte transmission/reception FADFH FAC5H Receive data 1 (R1) Receive data 4 (R4) SIO1 Receive data 2 (R2) Receive data 3 (R3) ADTP Transmit data 4 (T4) –1...
Page 407 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) Basic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when any data is written to the serial I/O shift register 1 (SIO1) while bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) is set to 1.
Page 408 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-12. Basic Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software Execution Set the transmission/reception operation interval time in ADTI Write any data to SIO1...
Page 409 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 0, RE = 0) in basic transmit mode, internal buffer RAM operates as follows. (i) Before transmission (see Figure 18-13 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1.
Page 410 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-13. Internal Buffer RAM Operation in 6-byte Transmission (in Basic Transmit Mode) (2/2) (b) 4th byte transmission point FADFH FAC5H Transmit data 1 (T1) SIO1 Transmit data 2 (T2) Transmit data 3 (T3) ADTP Transmit data 4 (T4) –1...
Page 411 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Repeat transmission mode In this mode, data stored in the internal buffer RAM is transmitted repeatedly. Serial transmission is started by writing any data to serial I/O shift register 1 (SIO1) when 1 is set in bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1).
Page 412 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-15. Repeat Transmission Mode Flowchart Start Write transmit data in internal buffer RAM Set ADTP to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software Execution Set the transmission/reception operation interval time in ADTI Write any data to SIO1...
Page 413 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, internal buffer RAM operates as follows. (i) Before transmission (see Figure 18-16 (a).) After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not transferred), transmit data 1 (T1) is transferred from the internal buffer RAM to SIO1.
Page 414 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-16. Internal Buffer RAM Operation in 6-byte Transmission (in Repeat Transmit Mode) (2/2) (b) Upon completion of transmission of 6 bytes FADFH FAC5H Transmit data 1 (T1) SIO1 Transmit data 2 (T2) Transmit data 3 (T3) ADTP Transmit data 4 (T4) Transmit data 5 (T5)
Page 415 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (d) Automatic transmission/reception suspending and restart Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of the serial operating mode register 1 (CSIM1) to 0. If during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (CSIE1) is set to 0. It is suspended upon completion of 8-bit data transfer.
Page 416 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (4) Synchronization control Busy control and strobe control are functions to synchronize transmission/reception between the master device and a slave device. By using these functions, a shift in bits being transmitted or received can be detected. (a) Busy control option Busy control is a function to keep the serial transmission/reception by the master device waiting while the busy signal output by a slave device to the master is active.
Page 417 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-19. Operation Timing when Busy Control Option Is Used (when BUSY0 = 0) SCK1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY Wait...
Page 418 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-20. Busy Signal and Wait Release (when BUSY0 = 0) SCK1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY 1.5 clock (min.)
Page 419 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 Figure 18-21. Operation Timing when Busy & Strobe Control Options Are Used (when BUSY0 = 0) SCK1 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 BUSY CSIIF1...
Page 420 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (c) Bit shift detection by busy signal During automatic transmission/reception, a bit shift of the serial clock of the slave device may occur because noise is superimposed on the serial clock signal output by the master device. Unless the strobe control option is used at this time, the bit shift affects transmission of the next byte.
Page 421 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (5) Automatic transmit/receive interval time When using the automatic transmit/receive function, the read/write operations from/to the internal buffer RAM are performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/ receive.
Page 422 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (a) When the automatic transmit/receive function is used by the internal clock If the bit 1 (CSIM11) of serial operating mode register (CSIM1) is set at (1), the internal clock operates. If the automatic transmit/receive function is operated by the internal clock, interval timing by CPU processing is as follows.
Page 423 CHAPTER 18 SERIAL INTERFACE CHANNEL 1 (b) When using automatic transmit/receive function with external clock The external clock is used when bit 1 (CSIM11) of the serial operating mode register 1 (CSIM1) is cleared to 0. To use the automatic transmit/receive function with the external clock, the external clock must be input such that the interval time is as follows: Table 18-3.
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Page 425: Chapter 19 Serial Interface Channel 2
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.1 Serial Interface Channel 2 Functions Serial interface channel 2 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode (with time-division transfer function) • 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out to reduce power consumption.
Page 426: Serial Interface Channel 2 Configuration
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.2 Serial Interface Channel 2 Configuration Serial interface channel 2 consists of the following hardware. Table 19-1. Serial Interface Channel 2 Configuration Item Configuration Register Transmit shift register (TXS) Receive shift register (RXS) Receive buffer register (RXB) Control register Serial operating mode register 2 (CSIM2) Asynchronous serial interface mode register (ASIM)
Page 427 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-1. Serial Interface Channel 2 Block Diagram Internal Bus Asynchronous Asynchronous Serial Interface Serial Interface Pin Serial Interface Mode Register Select Register Status Register Direction Receive Buffer SIPS21 SIPS20 RXE PS1 PS0 CL SL ISRM Register Control Circuit...
Page 428 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-2. Baud Rate Generator Block Diagram CSIE2 Start Bit Sampling Clock 5-Bit Counter ASCK/SCK2/P72 Transmit Clock Selector to f Match TPS0 to TPS3 MDL0 to MDL3 CSCK Decoder Receive Match Clock 5-Bit Counter Start Bit Detection TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0...
Page 429 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (1) Transmit shift register (TXS) This register is used to set the transmit data. The data written in the TXS is transmitted as serial data. If the data length is specified as 7 bits, bits 0 to 6 of the data written in the TXS are transferred as transmit data.
Page 430: Serial Interface Channel 2 Control Registers
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.3 Serial Interface Channel 2 Control Registers Serial interface channel 2 is controlled by the following five registers. • Serial Operating Mode Register 2 (CSIM2) • Asynchronous Serial Interface Mode Register (ASIM) • Asynchronous Serial Interface Status Register (ASIS) •...
Page 431 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Asynchronous serial interface mode register (ASIM) This register is set when serial interface channel 2 is used in the asynchronous serial interface mode. ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM to 00H.
Page 432 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19-2. Serial Interface Channel 2 Operating Mode Settings (1/2) (1) Operation Stop Mode ASIM CSIM2 SIPS PM72 P72 PM70 P70 PM71 P71 PM23 PM24 Start Shift P72/SCK2 P70/SI2/ P71/SO2/ P23/STB/ P24/BUSY/ Clock /ASCK Pin RxD0 Pin TxD0 Pin TxD1 Pin...
Page 433 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Table 19-2. Serial Interface Channel 2 Operating Mode Settings (2/2) (3) Asynchronous Serial Interface Mode ASIM CSIM2 SIPS PM70 P70 PM71 P71 PM72 P72 Start Shift P72/SCK2 PM23 PM24 P70/SI2/ P71/SO2/ P23/STB/ P24/BUSY/ Clock /ASCK Pin RxD0 Pin TxD0 Pin...
Page 434 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) Asynchronous serial interface status register (ASIS) This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. ASIS is read with a 1-bit or 8-bit memory manipulation instruction. In 3-wire serial I/O mode, the contents of ASIS are undefined.
Page 435 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (4) Baud rate generator control register (BRGC) This register sets the serial clock for serial interface channel 2. BRGC is set with an 8-bit memory manipulation instruction. RESET input clears BRGC to 00H. Figure 19-6. Baud Rate Generator Control Register Format (1/2) Symbol Address After Reset...
Page 436 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-6. Baud Rate Generator Control Register Format (2/2) TPS3 TPS2 TPS1 TPS0 5-Bit Counter Source Clock Selection MCS = 1 MCS = 0 (4.9 kHz) (2.4 kHz) (5.0 MHz) (2.5 MHz) (2.5 MHz) (1.25 MHz) (1.25 MHz) (625 kHz)
Page 437 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (a) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clocks generated by scaling the main system clock.
Page 438 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. ASCK [Baud rate] = [Hz]...
Page 439 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (5) Serial interface pin select register (SIPS) This register selects input/output pins when the serial interface channel 2 is used in the asynchronous serial interface mode (with time-division transfer function). SIPS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SIPS to 00H.
Page 440: Serial Interface Channel 2 Operation
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4 Serial Interface Channel 2 Operation The operating mode of serial interface channel 2 has the following three types. • Operation stop mode • Asynchronous serial interface (UART) mode (with time-division transfer function) • 3-wire serial I/O mode 19.4.1 Operation stop mode In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.
Page 441 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM to 00H. Symbol Address After Reset ASIM ISRM SCK FF70H Receive Operation Control Receive operation stopped Receive operation enabled Transmit Operation Control...
Page 442: Asynchronous Serial Interface (Uart) Mode (With Time-Division Transfer Function)
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.2 Asynchronous serial interface (UART) mode (with time-division transfer function) In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
Page 443 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM to 00H. Symbol Address After Reset ASIM ISRM SCK FF70H Clock Selection in Asynchronous Serial Interface Mode Input clock from off-chip to ASCK pin Dedicated baud rate generator output...
Page 444 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Asynchronous serial interface status register (ASIS) ASIS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIS to 00H. Symbol Address After Reset ASIS FF71H Overrun Error Flag Overrun error not generated Overrun error generated Note 1 (When next receive operation is completed before...
Page 445 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input clears BRGC to 00H. Symbol Address After Reset BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection...
Page 446 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 5-Bit Counter Source Clock Selection MCS = 1 MCS = 0 (4.9 kHz) (2.4 kHz) (5.0 MHz) (2.5 MHz) (2.5 MHz) (1.25 MHz) (1.25 MHz) (625 kHz) (625 kHz) (313 kHz) (313 kHz) (156 kHz) (156 kHz)
Page 447 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin. (i) Generation of baud rate transmit/receive clock by means of main system clock The transmit/receive clock is generated by scaling the main system clock.
Page 448 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression. ASCK [Baud rate] = [Hz]...
Page 449 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (e) Serial interface pin select register (SIPS) SIPS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SIPS to 00H. To select input/output pins, the port mode register and the output latch of the port must be set. For details, refer to Table 19-2 Serial Interface Channel 2 Operating Mode Settings.
Page 450 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation (a) Data format The transmit/receive data format is as shown in Figure 19-8. Figure 19-8. Asynchronous Serial Interface Transmit/Receive Data Format One Data Frame Start Parity Stop Bit Character Bit One data frame consists of the following bits: •...
Page 451 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Parity types and operation The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected.
Page 452 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Transmission A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically. When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is generated.
Page 453 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (d) Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (to 1), a receive operation is enabled and sampling of the RxD0 (RxD1) pin input is started. RxD0 (RxD1) pin input sampling is performed using the serial clock specified by ASIM. When the RxD0 (RxD1) pin input becomes low, the 5-bit counter of the baud rate generator (see Figure 19-2) starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output.
Page 454 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (e) Receive errors Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. The data reception result error flag is set in the asynchronous serial interface status register (ASIS) and a receive error interrupt request (INTSER) is generated.
Page 455 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (3) UART mode cautions (a) When the transmission under execution has been stopped by clearing bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) to 0, be sure to set the transmit shift register (TXS) to FFH, then set the TXE to 1 before executing the next transmission.
Page 456: 3-Wire Serial I/O Mode
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.3 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, 17K Series, etc. Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
Page 457 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (b) Asynchronous serial interface mode register (ASIM) ASIM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM to 00H. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM. Symbol Address After Reset...
Page 458 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (c) Baud rate generator control register (BRGC) BRGC is set with an 8-bit memory manipulation instruction. RESET input clears BRGC to 00H. Symbol Address After Reset BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection...
Page 459 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 TPS3 TPS2 TPS1 TPS0 5-Bit Counter Source Clock Selection MCS = 1 MCS = 0 (4.9 kHz) (2.4 kHz) (5.0 MHz) (2.5 MHz) (2.5 MHz) (1.25 MHz) (1.25 MHz) (625 kHz) (625 kHz) (313 kHz) (313 kHz) (156 kHz) (156 kHz)
Page 460 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below. BRGC setting is not required if an external serial clock is used. (i) When the baud rate generator is not used: Select a serial clock frequency with TPS0 to TPS3.
Page 461 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock. Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock SCK2.
Page 462 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-14. Circuit of Switching in Transfer Bit Order Internal Bus LSB-first MSB-first Read/Write Gate Read/Write Gate SO2 Latch Transmit Shift Register (TXS/SIO2) SCK2 Start bit switching is realized by switching the bit order for data write to SIO2. The SIO2 shift order remains unchanged.
Page 463: Restrictions In Uart Mode
CHAPTER 19 SERIAL INTERFACE CHANNEL 2 19.4.4 Restrictions in UART mode In the UART mode, the reception completion interrupt request (INTSR) occurs a certain time after the reception error interrupt (INTSER) has occurred and then cleared. Consequently, the following phenomenon may occur. •...
Page 464 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 Figure 19-16. Receive Buffer Register Read Disable Period STOP D (Input) Parity START INTSR INTSER (When framing/ overrun error occurs) INTSER (When parity error occurs) T1 : Time of one data of baud rate selected by baud rate generator control register (BRGC) (1/baud rate) T2 : Time of 2 clocks of source clock (f ) of 5-bit counter selected by BRGC •...
Page 465 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 [Example] UART Receive Error Interrupt (INTSER) Processing Main Processing INTSER occurs Instructions of Seven CPU Clocks (MIN.) 2,205 CPU (Time from generation of clocks (MIN.) interrupt request to processing) are necessary. MOV A, RXB RETI...
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Page 467: Chapter 20 Real-Time Output Port
CHAPTER 20 REAL-TIME OUTPUT PORT 20.1 Real-Time Output Port Functions Data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with the generation of a timer interrupt request or external interrupt request, then output externally. This is called the real-time output function.
Page 468: Real-Time Output Port Configuration
CHAPTER 20 REAL-TIME OUTPUT PORT 20.2 Real-Time Output Port Configuration The real-time output port consists of the following hardware. Table 20-1. Real-time Output Port Configuration Item Configuration Register Real-time output buffer register (RTBL, RTBH) Control register Port mode register 12 (PM12) Real-time output port mode register (RTPM) Real-time output port control register (RTPC) Figure 20-1.
Page 469 CHAPTER 20 REAL-TIME OUTPUT PORT (1) Real-time output buffer register (RTBL, RTBH) Addresses of RTBL and RTBH are mapped individually in the Special function register (SFR) area as shown in Figure 20-2. When specifying 4 bits × 2 channels as the operating mode, data are set individually in RTBL and RTBH. When specifying 8 bits ×...
Page 470: Real-Time Output Port Control Registers
CHAPTER 20 REAL-TIME OUTPUT PORT 20.3 Real-Time Output Port Control Registers The following three registers control the real-time output port. • Port mode register 12 (PM12) • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Port mode register 12 (PM12) This register sets the input or output mode of port 12 pins (P120 to P127) which are multiplexed with real- time output pins (RTP0 to RTP7).
Page 471 CHAPTER 20 REAL-TIME OUTPUT PORT (3) Real-time output port control register (RTPC) This register sets the real-time output port operating mode and output trigger. Table 20-3 shows the relation between the operating mode of the real-time output port and output trigger. RTPC is set with a 1-bit or 8-bit memory manipulation instruction.
Page 472 [MEMO]...
Page 473: Chapter 21 Interrupt And Test Functions
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. It generates a standby release signal.
Page 474: Interrupt Sources And Configuration
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.2 Interrupt Sources and Configuration A total of 21 non-maskable, maskable, and software interrupts are provided as the interrupt sources (see Table 21-1). Table 21-1. Interrupt Source List (1/2) Vector Basic Interrupt Default Interrupt Source Internal/ Table Configuration...
Page 475 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Table 21-1. Interrupt Source List (2/2) Vector Basic Interrupt Default Interrupt Source Internal/ Table Configuration Note 1 Type Priority External Note 2 Name Trigger Address Type Maskable INTTM3 Reference time interval signal from Internal 001EH watch timer INTTM00...
Page 476 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal Bus Vector Table Priority Control Interrupt Address Circuit Request Generator Standby Release Signal (B) Internal maskable interrupt Internal Bus Vector Table Priority Control Address Interrupt...
Page 477 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) Internal Bus External Interrupt Mode Register (INTM0, INTM1) Vector Table Priority Control Address Interrupt Edge Circuit Generator Request Detector Standby Release Signal (E) Software interrupt Internal Bus...
Page 478: Interrupt Function Control Registers
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L) • Interrupt mask flag register (MK0L, MK0H, MK1L) •...
Page 479 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L) The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 480 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L, MK0H, and MK1L are set with a 1-bit or an 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
Page 481 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Priority specify flag registers (PR0L, PR0H, and PR1L) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L, PR0H, and PR1L are set with a 1-bit or an 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
Page 482 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (4) External interrupt mode register (INTM0, INTM1) These registers set the valid edge for INTP0 to INTP5. INTM0 specifies the valid edges of interrupt pins INTP0 to INTP2, and INTM1 specifies the valid edges of INTP3 to INTP5.
Page 483 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-6. External Interrupt Mode Register 1 Format After Address Symbol Reset INTM1 ES61 ES60 ES51 ES50 ES41 ES40 FFEDH ES41 ES40 INTP3 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 ES50 INTP4 Valid Edge Selection...
Page 484 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (5) Sampling clock select register (SCS) This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlled data reception is carried out using INTP0, digital noise is eliminated with sampling clocks. SCS is set with an 8-bit memory manipulation instruction.
Page 485 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS When the sampled INTP0 input level is active twice in succession, the noise eliminator sets the interrupt request flag (PIF0) to 1. Figure 21-8 shows the input/output timing of the noise eliminator. Figure 21-8. Noise Eliminator Input/Output Timing (During Rising Edge Detection) (a) When input is less than the sampling cycle (t Sampling Clock INTP0...
Page 486 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped.
Page 487: Interrupt Servicing Operations
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4 Interrupt Servicing Operations 21.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents of acknowledged interrupt are saved in the stacks, PSW and PC, in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched.
Page 488 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-10. Non-Maskable Interrupt Request Occurrence and Acknowledge Flowchart Start WDTM4 = 1 (with watchdog timer mode selected)? Interval timer Overflow in WDT? WDTM3 = 0 (with non-maskable interrupt selected)? Reset processing Interrupt request generation WDT interrupt servicing? Interrupt request held pending...
Page 489 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-12. Non-Maskable Interrupt Request Acknowledge Operation If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request <1> Execution NMI Request <1> NMI Request <2> Reserve NMI Request <2>...
Page 490: Maskable Interrupt Request Acknowledge Operation
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).
Page 491 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-13. Interrupt Request Acknowledge Processing Algorithm Start × × IF = 1? Yes (Interrupt Request Generation) × × MK = 0? Interrupt request reserve Yes (High priority) × × PR = 0? No (Low Priority) Any high- priority interrupt among simultaneously generated...
Page 492 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-14. Interrupt Request Acknowledge Timing (Minimum Time) 6 Clocks PSW and PC Save, Interrupt CPU Processing Instruction Instruction Jump to Interrupt Servicing Servicing Program × × IF (× × PR = 1) 8 Clocks ×...
Page 493: Software Interrupt Request Acknowledge Operation
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.3 Software interrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled. If a software interrupt request is acknowledged, the contents of acknowledged interrupts are saved in the stacks, program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0 and the contents of the vector tables (003EH and 003FH) are loaded into PC and branched.
Page 494 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-16. Multiple Interrupt Example (1/2) Example 1. Two multiple interrupts are acknowledged. Main Processing INTxx INTyy INTzz Servicing Servicing Servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 495 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS Figure 21-16. Multiple Interrupt Example (2/2) Example 3. Multiple interrupt is not acknowledged because an interrupt is not enabled. Main Processing INTxx INTyy Servicing Servicing IE = 0 INTyy (PR = 0) INTxx (PR = 0) RETI IE = 0 1 Instruction...
Page 496: Interrupt Request Reserve
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.4.5 Interrupt request reserve Even if an interrupt request is generated, some instructions reserve interrupt acknowledge while the current instruction is executed and until execution of the next instruction is completed. The instruction that reserve interrupt requests (interrupt request reserve) are shown below.
Page 497: Test Functions
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS 21.5 Test Functions When the watch timer overflows, port 4 falling edge is detected, an internal test input flag is set to 1, and the standby release signal is generated. Unlike the interrupt function, vectored processing is not performed. There are two test input factors as shown in Table 21-5.
Page 498 CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (1) Interrupt request flag register 1L (IF1L) It indicates whether a watch timer overflow is detected or not. IF1L is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears IF1L to 00H. Figure 21-19.
Page 499: Test Input Signal Acknowledge Operation
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS (3) Key return mode register (KRM) This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge detection). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM to 02H.
Page 500 [MEMO]...
Page 501: Chapter 22 External Device Expansion Function
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.1 External Device Expansion Functions The external device expansion functions connect external devices to are as other than the internal ROM, RAM, and SFR. Connection of external devices uses ports 4 to 6. Ports 4 to 6 control address/data, read/write strobe, wait, address strobe etc.
Page 502 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Memory maps when using the external device expansion function are as follows. Figure 22-1. Memory Map when Using External Device Expansion Function (1/3) (a) Memory map of µ PD780053 and 780053Y, (b) Memory map of µ PD780054 and 780054Y, and µ...
Page 503 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (2/3) (c) Memory map of µ PD780055 and 780055Y, (d) Memory map of µ PD780056 and 780056Y, and µ PD780058, 780058Y, 78F0058, and and µ PD780058, 780058Y, 78F0058, and 78F0058Y with internal ROM (flash memory) 78F0058Y with internal ROM (flash memory) set to 40 KB...
Page 504 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-1. Memory Map when Using External Device Expansion Function (3/3) (e) µ PD780058, 780058Y, 78F0058, 78F0058Y µ PD780058, 780058Y, 78F0058, 78F0058Y Memory map when internal ROM (flash Memory map when internal ROM (flash memory) size is 56 Kbytes memory) size is 60 Kbytes FFFFH...
Page 505: External Device Expansion Function Control Register
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register (MM) and memory size switching register (IMS). (1) Memory expansion mode register (MM) MM sets the wait count and external expansion area, and also sets the input/output of port 4. MM is set with a 1-bit memory or 8-bit memory manipulation instruction.
Page 506 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION (2) Memory size switching register (IMS) This register specifies the internal memory size. In principle, use IMS in a default status. However, when using the external device expansion function with the µ PD780058, 780058Y, set the IMS so that the internal ROM capacity is 56 Kbytes or lower.
Page 507: External Device Expansion Function Timing
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows. (1) RD pin (Alternate function: P64) Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from external memory.
Page 508 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-4. Instruction Fetch from External Memory (a) No wait (PW1, PW0 = 0, 0) setting ASTB AD0 to AD7 Lower Address Operation Code A8 to A15 Higher Address (b) Wait (PW1, PW0 = 0, 1) setting ASTB AD0 to AD7 Lower Address...
Page 509 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-5. External Memory Read Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB AD0 to AD7 Lower Address Read Data A8 to A15 Higher Address (b) Wait (PW1, PW0 = 0, 1) setting ASTB AD0 to AD7 Lower Address...
Page 510 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-6. External Memory Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z AD0 to AD7 Lower Address Write Data Higher Address A8 to A15 (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Lower Address...
Page 511 CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION Figure 22-7. External Memory Read Modify Write Timing (a) No wait (PW1, PW0 = 0, 0) setting ASTB Hi-Z Lower Address Read Data Write Data AD0 to AD7 A8 to A15 Higher Address (b) Wait (PW1, PW0 = 0, 1) setting ASTB Hi-Z Read Data...
Page 512: Example Of Connection With Memory
CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION 22.4 Example of Connection with Memory This section provides µ PD780054 and external memory connection examples in Figure 22-8. SRAMs are used as the external memory in these diagrams. In addition, the external device expansion function is used in the full- address mode, and the address from 0000H to 7FFFH (32 Kbytes) are allocated for internal ROM, and the addresses after 8000H for SRAM.
Page 513: Chapter 23 Standby Function
CHAPTER 23 STANDBY FUNCTION 23.1 Standby Function and Configuration 23.1.1 Standby function The standby function is designed to decrease power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. System clock oscillator continues oscillation.
Page 514: Standby Function Control Register
CHAPTER 23 STANDBY FUNCTION 23.1.2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 515: Standby Function Operations
CHAPTER 23 STANDBY FUNCTION 23.2 Standby Function Operations 23.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the subsystem clock. The operating status in the HALT mode is described below.
Page 516 CHAPTER 23 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released with the following four types of sources. (a) Release by unmasked interrupt request If an unmasked interrupt request is generated, the HALT mode is released. If interrupt request acknowledgement is enabled, vectored interrupt service is carried out.
Page 517 CHAPTER 23 STANDBY FUNCTION (d) Release by RESET input If the RESET signal is input, the HALT mode is released. As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 23-3. HALT Mode Release by RESET Input Wait HALT : 26.2 ms)
Page 518: Stop Mode
CHAPTER 23 STANDBY FUNCTION 23.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock. Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V via a pull-up resistor to minimize the leakage current at the crystal oscillator.
Page 519 CHAPTER 23 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released with the following three types of sources. (a) Release by unmasked interrupt request If an unmasked interrupt request is generated, the STOP mode is released. If interrupt request acknowledgement is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
Page 520 CHAPTER 23 STANDBY FUNCTION (c) Release by RESET input If the RESET signal is input, the STOP mode is released and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 23-5. STOP Mode Release by RESET Input Wait STOP : 26.2 ms)
Page 521: Chapter 24 Reset Function
CHAPTER 24 RESET FUNCTION 24.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input by RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 522 CHAPTER 24 RESET FUNCTION Figure 24-2. Reset Timing by RESET Input Oscillation Reset Period Normal Operation Normal Operation Stabilization (Oscillation (Reset Processing) Time Wait Stop) RESET Internal Reset Signal Delay Delay Hi-Z Port Pin Figure 24-3. Reset Timing due to Watchdog Timer Overflow Normal Operation Reset Period Oscillation...
Page 523 CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status After Reset (1/2) Hardware Status after Reset Note 1 Program counter (PC) The contents of reset vector tables (0000H and 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2...
Page 524 CHAPTER 24 RESET FUNCTION Table 24-1. Hardware Status after Reset (2/2) Hardware Status after Reset Watch timer Mode control register (TMC2) Clock select register (TCL2) Watchdog timer Mode register (WDTM) Serial interface Clock select register (TCL3) Shift registers (SIO0, SIO1) Undefined Mode registers (CSIM0, CSIM1, CSIM2) Serial bus interface control register (SBIC)
Page 525: Chapter 25 Rom Correction
CHAPTER 25 ROM CORRECTION 25.1 ROM Correction Functions The µ PD780058, 780058Y Subseries can replace part of a program in the mask ROM with a program in the internal expansion RAM. Instruction bugs found in the mask ROM can be avoided, and program flow can be changed by using the ROM correction.
Page 526 CHAPTER 25 ROM CORRECTION (1) Correction address registers 0 and 1 (CORAD0, CORAD1) These registers set the start address (correction address) of the instruction(s) to be corrected in the mask ROM. The ROM correction corrects two places (max.) of the program. Addresses are set to two registers, CORAD0 and CORAD1.
Page 527: Rom Correction Control Registers
CHAPTER 25 ROM CORRECTION 25.3 ROM Correction Control Registers The ROM correction is controlled with the correction control register (CORCN). (1) Correction control register (CORCN) This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1.
Page 528: Rom Correction Application
CHAPTER 25 ROM CORRECTION 25.4 ROM Correction Application (1) Store the correction address and instruction after correction (patch program) to nonvolatile memory (such as EEPROM ) outside the microcontroller. When two places should be corrected, store the branch destination judgment program as well. The branch destination judgment program checks which one of the addresses set to correction address registers 0 and 1 (CORAD0 or CORAD1) generates the correction branch.
Page 529 CHAPTER 25 ROM CORRECTION (2) Assemble in advance the initialization routine as shown in Figure 25-5 to correct the program. Figure 25-5. Initialization Routine Initialization ROM Correction Is ROM Note correction used ? Load the contents of external nonvolatile memory into internal expansion RAM Correction address register setting ROM correction operation enabled...
Page 530 CHAPTER 25 ROM CORRECTION Figure 25-6. ROM Correction Operation Internal ROM Program Start Does fetch address match with correction address? ROM Correction Set Correction Status Flag Correction Branch (branch to address F7FDH) Correction Program Execution...
Page 531: Rom Correction Usage Example
CHAPTER 25 ROM CORRECTION 25.5 ROM Correction Usage Example The example of ROM correction when the instruction at address 1000H “ADD A, #1” is changed to “ADD A, #2” is as follows. Figure 25-7. ROM Correction Usage Example Internal Expansion RAM Internal ROM F400H 0000H...
Page 532: Program Execution Flow
CHAPTER 25 ROM CORRECTION 25.6 Program Execution Flow Figures 25-8 and 25-9 show the program transition diagrams when the ROM correction is used. Figure 25-8. Program Transition Diagram (When One Place Is Corrected) FFFFH F7FFH BR !JUMP F7FDH Correction Program JUMP Internal ROM Correction Place...
Page 533 CHAPTER 25 ROM CORRECTION Figure 25-9. Program Transition Diagram (When Two Places Are Corrected) FFFFH F7FFH BR !JUMP F7FDH Correction Program 2 yyyyH Correction Program 1 xxxxH Destination Judge Program JUMP Internal ROM Correction Place 2 Internal ROM Correction Place 1 Internal ROM 0000H (1) Branches to address F7FDH when fetch address matches correction address...
Page 534: Rom Correction Cautions
CHAPTER 25 ROM CORRECTION 25.7 ROM Correction Cautions (1) Address values set in correction address registers 0 and 1 (CORAD0, CORAD1) must be addresses where instruction codes are stored. (2) Correction address registers 0 and 1 (CORAD0, CORAD1) should be set when the correction enable flag (COREN0, COREN1) is 0 (when the correction branch is in disabled state).
Page 535: Chapter 26 Μ Pd78F0058, 78F0058Y
CHAPTER 26 µ PD78F0058, 78F0058Y The µ PD78F0058 and 78F0058Y have a flash memory whose contents can be written, erased, rewritten with the device mounted on a PC board. Table 26-1 lists the differences between the flash memory versions ( µ PD78F0058 and 78F0058Y) and the mask ROM versions ( µ...
Page 536: Memory Size Switching Register
CHAPTER 26 µ PD78F0058, 78F0058Y 26.1 Memory Size Switching Register The µ PD78F0058 and 78F0058Y allow users to define its internal ROM size using the memory size switching register (IMS), so that the same memory mapping as that of a mask ROM version with a different-size internal ROM is possible.
Page 537: Internal Expansion Ram Size Switching Register
CHAPTER 26 µ PD78F0058, 78F0058Y 26.2 Internal Expansion RAM Size Switching Register The µ PD78F0058 and 78F0058Y allow users to define its internal expansion RAM size by using the internal expansion RAM size switching register (IXS), so that the same memory mapping as that of a mask ROM version with a different-size internal expansion RAM is possible.
Page 538: Flash Memory Programming
CHAPTER 26 µ PD78F0058, 78F0058Y 26.3 Flash Memory Programming Data can be written to the flash memory with the device mounted on the target system (on-board). Write data to the flash memory by connecting the dedicated flash programmer (Flashpro II) to the host machine and target system. Remark Flashpro II is a product made by Naitou Densei Machidaseisakusho Co., Ltd.
Page 539: Flash Memory Programming Function
CHAPTER 26 µ PD78F0058, 78F0058Y Figure 26-3. Communication Mode Selecting Format 10 V RESET 26.3.2 Flash memory programming function Data is written to the flash memory by transmitting or receiving commands and data in the selected communication mode. The major functions are listed in Table 26-5. Table 26-5.
Page 540: Connecting Flashpro
CHAPTER 26 µ PD78F0058, 78F0058Y 26.3.3 Connecting Flashpro II Connection between the Flashpro II and µ PD78F0058 (or µ PD78F0058Y) differs depending on the communication mode. Figures 26-4 to 26-6 show the connections in the respective communication modes. Figure 26-4. Connection of Flashpro II in 3-wire Serial I/O Mode µ...
Page 541 CHAPTER 26 µ PD78F0058, 78F0058Y Figure 26-6. Connection of Flashpro II in Pseudo 3-wire Serial I/O Mode µ Flashpro II PD78F0058, 78F0058Y RESET RESET P32 (serial clock) P30 (serial input) P31 (serial output)
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Page 543: Chapter 27 Instruction Set Outline
CHAPTER 27 INSTRUCTION SET OUTLINE This chapter describes each instruction set of the µ PD780058 and 780058Y Subseries as list table. For details of its operation and operation code, refer to the separate document 78K/0 Series User’s Manual — Instructions (U12326E).
Page 544: Legends Used In Operation List
CHAPTER 27 INSTRUCTION SET OUTLINE 27.1 Legends Used in Operation List 27.1.1 Operand identifiers and description methods Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.
Page 545: Description Of Operation Column
CHAPTER 27 INSTRUCTION SET OUTLINE 27.1.2 Description of operation column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair...
Page 546: Operation List
CHAPTER 27 INSTRUCTION SET OUTLINE 27.2 Operation List Clock Flag Instruction Mnemonic Operands Byte Operation Group Note 1 Note 2 Z AC CY r ← byte 8-bit data r, #byte – transfer (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte –...
Page 547 CHAPTER 27 INSTRUCTION SET OUTLINE Clock Flag Instruction Mnemonic Operands Byte Operation Group Note 1 Note 2 Z AC CY rp ← word 16-bit MOVW rp, #word – data (saddrp) ← word saddrp, #word transfer sfrp ← word sfrp, #word –...
Page 548 CHAPTER 27 INSTRUCTION SET OUTLINE Clock Flag Instruction Mnemonic Operands Byte Operation Group Note 1 Note 2 Z AC CY A, CY ← A – byte × × × 8-bit A, #byte – operation (saddr), CY ← (saddr) – byte ×...
Page 549 CHAPTER 27 INSTRUCTION SET OUTLINE Clock Flag Instruction Mnemonic Operands Byte Operation Group Note 1 Note 2 Z AC CY A ← A byte × 8-bit A, #byte – operation (saddr) ← (saddr) byte × saddr, #byte A ← A r ×...
Page 550 CHAPTER 27 INSTRUCTION SET OUTLINE Clock Flag Instruction Mnemonic Operands Byte Operation Group Note 1 Note 2 Z AC CY AX, CY ← AX + word × × × 16-bit ADDW AX, #word – operation AX, CY ← AX – word ×...
Page 551 CHAPTER 27 INSTRUCTION SET OUTLINE Clock Flag Instruction Mnemonic Operands Byte Operation Group Note 1 Note 2 Z AC CY CY ← CY (saddr.bit) × AND1 CY, saddr.bit manipu- CY ← CY sfr.bit × CY, sfr.bit – late CY ← CY A.bit ×...
Page 552 CHAPTER 27 INSTRUCTION SET OUTLINE Clock Flag Instruction Mnemonic Operands Byte Operation Group Note 1 Note 2 Z AC CY (SP – 1) ← (PC + 3) , (SP – 2) ← (PC + 3) Call/return CALL !addr16 – PC ← addr16, SP ← SP – 2 (SP –...
Page 553 CHAPTER 27 INSTRUCTION SET OUTLINE Clock Flag Instruction Mnemonic Operands Byte Operation Group Note 1 Note 2 Z AC CY PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Condi- saddr.bit, $addr16 tional PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 –...
Page 554: Instructions Listed By Addressing Type
CHAPTER 27 INSTRUCTION SET OUTLINE 27.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ...
Page 555 CHAPTER 27 INSTRUCTION SET OUTLINE Second Operand [HL + byte] Note #byte saddr !addr16 [DE] [HL] [HL + B] $addr16 None First Operand [HL + C] ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC SUBC SUBC ADDC SUBC B, C...
Page 556 CHAPTER 27 INSTRUCTION SET OUTLINE (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand Note #word sfrp saddrp !addr16 None 1st Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp...
Page 557 CHAPTER 27 INSTRUCTION SET OUTLINE (4) Call/instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP...
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Page 559: Appendix A Differences Among Μ Pd78054, 78058F, And 780058 Subseries
APPENDIX A DIFFERENCES AMONG µ PD78054, 78058F, AND 780058 SUBSERIES Table A-1 shows the major differences among the µ PD78054, 78058F, and 780058 Subseries. Table A-1. Major Differences Among µ PD78054, 78058F, and 780058 Subseries (1/2) µ PD78054 Subseries µ PD78058F Subseries µ...
Page 560 APPENDIX A DIFFERENCES AMONG µ PD78054, 78058F, AND 780058 SUBSERIES Table A-1. Major Differences among µ PD78054, 78058F, and 780058 Subseries (2/2) µ PD78054 Subseries µ PD78058F Subseries µ PD780058 Subseries Product Name Item Package • 80-pin plastic QFP • 80-pin plastic QFP •...
Page 561: Appendix B Development Tools
APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µ PD780058 and 780058Y Subseries. Figure B-1 shows the configuration of the development tools.
Page 562 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (1/2) (1) When using the in-circuit emulator IE-78K0-NS Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tool • System simulator •...
Page 563 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (2/2) (1) When using the in-circuit emulator IE-78001-R-A Language Processing Software • Assembler package • C compiler package • C library source file • Device file Debugging Tool • System simulator •...
Page 564: Language Processing Software
APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software This assembler converts programs written in mnemonics into an object codes RA78K/0 executable with a microcontroller. Assembler Package Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization. This assembler should be used in combination with an optical device file (DF780058).
Page 565: Flash Memory Writing Tools
APPENDIX B DEVELOPMENT TOOLS µ S××××RA78K0 µ S××××CC78K0 µ S××××DF780058 µ S××××CC78K0-L ×××× Host Machine Supply Medium Notes 1, 2 AA13 PC-9800 series Windows (Japanese version) 3.5-inch 2HD FD Notes 1, 2 AB13 IBM PC/AT and its compatibles Windows (Japanese version) 3.5-inch 2HC FD Notes 1, 2 BB13...
Page 566: Debugging Tools
APPENDIX B DEVELOPMENT TOOLS B.3 Debugging Tools B.3.1 Hardware (1/2) (1) When using the in-circuit emulator IE-78K0-NS Note This is an in-circuit emulator for debugging the hardware and software when an IE-78K0-NS application system using the 78K/0 Series is developed. It supports the integrated In-circuit Emulator debugger (ID78K0-NS).
Page 567 APPENDIX B DEVELOPMENT TOOLS B.3.1 Hardware (2/2) (2) When using the in-circuit emulator IE-78001-R-A Note This is an in-circuit emulator for debugging the hardware and software when an IE-78001-R-A application system using the 78K/0 Series is developed. It supports the integrated In-circuit Emulator debugger (ID78K0).
Page 568: Software
APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/2) SM78K0 This simulator can debug target system at C source level or assembler level while simulating System Simulator operation of target system on host machine. SM78K0 runs on Windows. By using SM78K0, logic and performance of application can be verified without in-circuit emulator independently of hardware development, so that development efficiency and software quality can be improved.
Page 569 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/2) Note This debugger is a control program to debug the 78K/0 Series microcontrollers. ID78K0-NS It adopts a graphical user interface, which is equivalent visually and operationally to Integrated Debugger Windows or OSF/Motif . It also has an enhanced debugging function for C language (supporting in-circuit emulator programs, and thus trace results can be displayed on screen in C-language level by using IE-78K0-NS)
Page 570: System-Upgrade Method From Former In-Circuit Emulator For 78K/0 Series To Ie-78001-R-A
Table B-1. System-up Method from Former In-Circuit Emulator for 78K/0 Series to the IE-78001-R-A Note In-Circuit Emulator Owned In-circuit Emulator Cabinet System-up Board to be Purchased IE-78000-R Required IE-78001-R-BK IE-78000-R-A Not required Note For upgrading a cabinet, send your in-circuit emulator to NEC.
Page 571 APPENDIX B DEVELOPMENT TOOLS Drawing and Footprint for Conversion Socket (EV-9200GC-80) Figure B-2. EV-9200GC-80 Drawing (For Reference Only) EV-9200GC-80 No.1 pin index EV-9200GC-80-G0 ITEM MILLIMETERS INCHES 18.0 0.709 14.4 0.567 14.4 0.567 18.0 0.709 4-C 2.0 4-C 0.079 0.031 0.236 16.0 0.63 18.7...
Page 572 APPENDIX B DEVELOPMENT TOOLS Figure B-3. EV-9200GC-80 Footprint (For Reference Only) Based on EV-9200GC-80 (2) Pad drawing (in mm) EV-9200GC-80-P1E ITEM MILLIMETERS INCHES 19.7 0.776 0.591 15.0 0.65 ± 0.02 × 19=12.35 ± 0.05 × 0.748=0.486 +0.001 +0.003 0.026 –0.002 –0.002 0.65 ±...
Page 573 APPENDIX B DEVELOPMENT TOOLS Drawing of Conversion Adapter (TGK-080SDW) Figure B-4. TGK-080SDW Drawing (For Reference Only) (unit: mm) TGK-080SDW (TQPACK080SD + TQSOCKET080SDW) Package dimension (unit: mm) M2 screw I J J J L L LM Protrusion : 4 places ITEM MILLIMETERS INCHES ITEM...
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Page 575: Appendix C Embedded Software
APPENDIX C EMBEDDED SOFTWARE This section describes the embedded software which are provided for the µ PD780058 and 780058Y Subseries to allow users to develop and maintain the application program for these subseries. Real-Time OS (1/2) Real-time OS conforming to µ ITRON specifications. RX78K/0 Real-time OS Tool (configurator) that is used to create nucleus of RX78K/0 and multiple information tables is supplied.
Page 576 APPENDIX C EMBEDDED SOFTWARE Real-Time OS (2/2) µ ITRON-specification subset OS. Nucleus of MX78K0 is supplied. MX78K0 This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next. <Precaution when using MX78K/0 in PC environment>...
Page 577: Appendix D Register Index
APPENDIX D REGISTER INDEX D.1 Register Index (Register Name) 16-bit timer mode control register (TMC0) ......................175 16-bit timer output control register (TOC0) ....................... 178 16-bit timer register (TM0) ..........................173 16-bit timer register (TMS) ..........................215 8-bit timer mode control register (TMC1) ......................218 8-bit timer output control register (TOC1) ......................
Page 578 APPENDIX D REGISTER INDEX Internal expansion RAM size switching register (IXS) ..................537 Interrupt mask flag register 0H (MK0H) ......................480 Interrupt mask flag register 0L (MK0L) ......................480 Interrupt mask flag register 1L (MK1L) ....................480, 498 Interrupt request flag register 0H (IF0H) ......................479 Interrupt request flag register 0L (IF0L) ......................
Page 579 APPENDIX D REGISTER INDEX Real-time output buffer register H (RTBH) ....................... 469 Real-time output buffer register L (RTBL) ......................469 Real-time output port control register (RTPC) ....................471 Real-time output port mode register (RTPM) ....................470 Receive buffer register (RXB) ........................... 429 Receive shift register (RXS) ..........................
Page 580: Register Index (Symbol)
APPENDIX D REGISTER INDEX D.2 Register Index (Symbol) ADCR: A/D conversion result register ......................259 ADIS: A/D converter input select register ....................263 ADM: A/D converter mode register ......................261 ADTC: Automatic data transmit/receive control register ..............386, 397 ADTI: Automatic data transmit/receive interval specify register ............
Page 581 APPENDIX D REGISTER INDEX MK1L: Interrupt mask flag register 1L ....................480, 498 Memory expansion mode register ..................144, 505 OSMS: Oscillation mode selection register ....................154 OSTS: Oscillation stabilization time select register ................... 514 Port 0 ............................... 124 Port 1 ............................... 126 P12: Port 12 .............................
Page 582 APPENDIX D REGISTER INDEX SIO0: Serial I/O shift register 0 ......................284, 336 SIO1: Serial I/O shift register 1 ......................... 382 SIPS: Serial interface pin select register ..................439, 449 SVA: Slave address register ......................284, 336 TCL0: Timer clock select register 0 ....................173, 250 TCL1: Timer clock select register 1 ......................
Page 583: Appendix E Revision History
APPENDIX E REVISION HISTORY The revision history of this edition is listed in the table below. “Chapter” indicates the chapter of the preceding edition where the revision was made. Edition Revisions Chapter Change of following block diagrams of ports: CHAPTER 6 PORT FUNCTIONS edition Figures 6-5 and 6-7 P20, P21, and P23 to P26 Block Diagram, Figures 6-6 and 6-8 P22 and P27 Block Diagram, Figure 6-9...
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Page 585 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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