Interrupts; Control Registers; Pwg2 Control Register - Epson S1C17W22 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS

2.5 Interrupts

PWG2 and CLG have a function to generate the interrupts shown in Table 2.5.1.
Interrupt
PWG2 mode transition
completion
IOSC oscillation stabiliza-
tion waiting completion
OSC1 oscillation stabili-
zation waiting completion
OSC3 oscillation stabili-
zation waiting completion
OSC1 oscillation stop
IOSC oscillation auto-
trimming completion
CLG provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the interrupt
controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For
more information on interrupt control, refer to the "Interrupt Controller" chapter.
Notes: • The PWGINTF.MODCMPIF bit is set to 1 if a condition shown above is met only when the
OSC1 oscillator circuit is operating regardless of RUN or SLEEP mode.
• When a transition, from RUN mode in which the system runs with a high-speed clock to
SLEEP mode in which the OSC1 oscillator circuit only operates (high-speed clocks are halt-
ed), has occurred in automatic mode, the PWGINTF.MODCMPIF bit is set to 1 after a lapse
of 1 ms from entering SLEEP mode. If the PWGINTE.MODCMPIE bit = 1 at this point, an
interrupt occurs and the CPU wakes up from SLEEP mode. When putting the CPU to SLEEP
mode with the OSC1 oscillator circuit activated, set the PWGINTE.MODCMPIE bit to 0.

2.6 Control Registers

PWG2 Control Register

Register name Bit
PWGCTL 15–8 –
7–3 –
2–0 PWGMOD[2:0]
Bits 15–3 Reserved
Bits 2–0 PWGMOD[2:0]
These bits control the PWG2 operating mode.
Note: The PWGCTL.PWGMOD[2:0] bits are set to 0x0 when 0x7, 0x6, 0x4, or 0x1 is written.
2-16
Table 2.5.1 PWG2 and CLG Interrupt Functions
Interrupt flag
PWGINTF.MODCMPIF When the transition from super economy mode to
another mode has completed, or when the transi-
tion from normal mode to economy mode has
completed in automatic mode (See Notes below.)
CLGINTF.IOSCSTAIF When the IOSC oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC1STAIF When the OSC1 oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC3STAIF When the OSC3 oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC1STPIF When OSC1CLK is stopped, or when the CLGOSC.
OSC1EN or CLGOSC1.OSDEN bit setting is al-
tered from 1 to 0.
CLGINTF.IOSCTEDIF When the IOSC oscillation auto-trimming opera-
tion has completed
Bit name Initial
0x00
0x00
0x0
Table 2.6.1 PWG2 Operating Mode
PWGCTL.PWGMOD[2:0] bits
0x7–0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Set condition
Reset R/W
– R –
– R
H0 R/WP
Operating mode
Reserved
Super economy mode
Reserved
Economy mode
Normal mode
Reserved
Automatic mode
S1C17W22/W23 TECHNICAL MANUAL
Clear condition
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Remarks
(Rev. 1.3)