Table of Contents
Advertisement
6 FUNCTIONS
6.3 Interrupts
When an interrupt occurs during program execution, the processor enters an interrupt handling state. The interrupt
handling state is a process by which the processor branches to the corresponding user's service routine for the
interrupt that occurred. The processor returns after branching and starts executing the program from where it left
off.
6.3.1 Priority of Interrupts
The interrupts supported by the S1C17 Core, their vector addresses and the priority of these interrupts are listed in
the table below.
Reset
Address misaligned interrupt
Debug interrupt
NMI
Software interrupt
Maskable external interrupt
When two or more interrupts occur simultaneously, they are processed in order of priority beginning with the one
that has the highest priority.
When an interrupt occurs, the processor disables interrupts that would occur thereafter and performs interrupt
handling. To support multiple interrupts (or another interrupt from within an interrupt), set the IE flag in the PSR
to 1 in the interrupt handler routine to enable interrupts during interrupt handling. Basically, even when multiple
interrupts are enabled, interrupts whose priorities are below the one set by the IL[2:0] bits in the PSR are not
accepted.
The debug interrupt does not use the vector table and the stack. The PC and PSR are saved in a specific area along
with R0.
The table below shows the addresses that are referenced when a debug interrupt occurs.
Table 6.3.1.2 Debug Interrupt Handler Start Address and Register Save Area
DBRAM set value + 0x00
DBRAM set value + 0x04
During debug interrupt handling, neither other interrupts nor multiple debug interrupts are accepted. They are kept
pending until the debug interrupt handling currently underway finishes.
6-6
Table 6.3.1.1 Vector Address and Priority of Interrupts
Interrupt
TTBR + 0x00 to TTBR + 0x7c
TTBR + 0x00 to TTBR + 0x7c
Address
0xfffc00
Seiko Epson Corporation
Vector address (Hex)
TTBR + 0x00
TTBR + 0x04
(0xfffc00)
TTBR + 0x08
Content
Debug interrupt handler start address
PC and PSR save area
R0 save area
(DBRAM: See Section 4.2.3)
Priority
High
Low
S1C17 CORE MANUAL
(REV. 1.2)
Advertisement
Table of Contents
