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Canceling HALT or SLEEP mode
The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and
put the CPU into RUN mode. This transition is executed even if the CPU does not accept the interrupt request.
• Interrupt request from a peripheral circuit
• NMI from the watchdog timer
• Debug interrupt
• Reset request
2.5 Interrupts
CLG has a function to generate the interrupts shown in Table 2.5.1.
Interrupt
IOSC oscillation stabiliza-
tion waiting completion
OSC3 oscillation stabili-
zation waiting completion
CLG provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the interrupt
controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For
more information on interrupt control, refer to the "Interrupt Controller" chapter.
2.6 Control Registers
PWG V
Regulator Control Register
D1
Register name
Bit
PWGVD1CTL
15–8 –
7–2 –
1–0 REGMODE[1:0]
Bits 15–2 Reserved
Bits 1–0
REGMODE[1:0]
These bits control the internal regulator operating mode.
PWGVD1CTL.REGMODE[1:0] bits
CLG System Clock Control Register
Register name
Bit
CLGSCLK
15
14
13–12 WUPDIV[1:0]
11–10 –
9–8 WUPSRC[1:0]
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Table 2.5.1 CLG Interrupt Functions
Interrupt flag
CLGINTF.IOSCSTAIF
When the IOSC oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC3STAIF When the OSC3 oscillation stabilization waiting
operation has completed after the oscillation starts
Bit name
Initial
0x00
0x00
0x0
Table 2.6.1 Internal Regulator Operating Mode
0x3
0x2
0x1
0x0
Bit name
Initial
WUPMD
–
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Set condition
Reset
R/W
–
R
–
–
R
H0
R/WP
Operating mode
Economy mode
Normal mode
Reserved
Automatic mode
Reset
R/W
0
H0
R/WP –
0
–
R
H0
R/WP
–
R
H0
R/WP
–
R
H0
R/WP
–
R
H0
R/WP
Clear condition
Writing 1
Writing 1
Remarks
Remarks
2-11
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