Clg Interrupt Flag Register - Epson S1C17M20 Technical Manual

Bits 5–4 OSC3INV[1:0]
These bits set the oscillation inverter gain of the OSC3 crystal/ceramic oscillator circuit.
Bit 3 OSC3STM
This bit controls the OSC3 internal oscillator auto-trimming function.
1 (WP): Start trimming
0 (WP): Stop trimming
1 (R): Trimming is executing.
0 (R): Trimming has finished. (Trimming operation inactivated.)
This bit is automatically cleared to 0 when trimming has finished.
Notes: • Do not use OSC3CLK as the system clock or peripheral circuit clocks while the
CLGOSC3.OSC3STM bit = 1.
• The auto-trimming function does not work if the OSC1 oscillator circuit is stopped. Make
sure the CLGINTF.OSC1STAIF bit is set to 1 before starting the trimming operation.
• Do not alter the CLGOSC3.OSC3FQ[1:0] bits while auto-trimming is being executed.
• Select the 32.768 kHz crystal oscillator for the OSC1 oscillator circuit when using the
auto-trimming function. The clock cannot be adjusted properly by the internal oscillator.
Bits 2–0 OSC3WT[2:0]
These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit.
Table 2.6.10 OSC3 Oscillation Stabilization Waiting Time Setting

CLG Interrupt Flag Register

Register name Bit
CLGINTF 15–8 –
7
6
5
4
3
2
1
0
Bits 15–6, 3 Reserved
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Table 2.6.9 OSC3 Oscillation Inverter Gain Setting
CLGOSC3.OSC3INV[1:0] bits
0x3
0x2
0x1
0x0
CLGOSC3.OSC3WT[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Bit name Initial
0x00
– 0x0
(reserved)
OSC1STPIF
OSC3TEDIF
–
OSC3STAIF
OSC1STAIF
IOSCSTAIF
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Inverter gain
Max.
↑
↓
Min.
Oscillation stabilization waiting time
65,536 clocks
16,384 clocks
4,096 clocks
1,024 clocks
256 clocks
64 clocks
16 clocks
4 clocks
Reset R/W
– R –
– R
0 H0 R
0 H0 R/W Cleared by writing 1.
0 H0 R/W
0 – R –
0 H0 R/W Cleared by writing 1.
0 H0 R/W
0 H0 R/W
Remarks
2-19