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2 POWER SUPPLY, RESET, AND CLOCKS
CLGOSC1A.OSC1WT[1:0] bits
ClG OSC3a Control Register
Register name
Bit
CLGOSC3A
15–8 –
7–6 –
5–4 INVN[1:0]
3–2 –
1–0 OSC3AWT[1:0]
Bits 15–6 Reserved
Bits 5–4
inVn[1:0]
These bits set the oscillation inverter gain of the OSC3A oscillator circuit.
Bits 3–2
Reserved
Bits 1–0
OSC3aWT[1:0]
These bits set the oscillation stabilization waiting time for the OSC3A oscillator circuit.
Table 2.
CLGOSC3A.OSC3AWT[1:0] bits
ClG interrupt Flag Register
Register name
Bit
CLGINTF
15–8 –
7–3 –
2
1
0
Bits 15–3 Reserved
Bit 2
OSC3aSTaiF
Bit 1
OSC1STaiF
Bit 0
OSC3BSTaiF
These bits indicate the oscillation stabilization waiting completion interrupt cause occurrence status in
each clock source.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
2-16
Table 2.
6.5 OSC1 Oscillation Stabilization Waiting Time Setting
0x3
0x2
0x1
0x0
Bit name
Initial
0x00
0x0
0x1
0x0
0x2
Table 2.
6.6 OSC3A Oscillation Inverter Gain Setting
CLGOSC3A.INVN[1:0] bits
0x3
0x2
0x1
0x0
6.7 OSC3A Oscillation Stabilization Waiting Time Setting
0x3
0x2
0x1
0x0
Bit name
Initial
0x00
0x0
OSC3ASTAIF
OSC1STAIF
OSC3BSTAIF
Seiko epson Corporation
Oscillation stabilization waiting time
OSC1B
32 clocks
65,536 clocks
16 clocks
16,384 clocks
8 clocks
4,096 clocks
Reserved
Reserved
Reset
R/W
–
R
–
–
R
H0
R/WP
–
R
H0
R/WP
Inverter gain
Max.
↑
↓
Min.
Oscillation stabilization waiting time
4,096 clocks
1,024 clocks
256 clocks
Reserved
Reset
R/W
–
R
–
–
R
0
H0
R/W
Cleared by writing 1.
0
H0
R/W
0
H0
R/W
OSC1A
Remarks
Remarks
S1C17F13 TeChniCal Manual
(Rev. 1.0)
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