Pwg2 Timing Control Register; Pwg2 Interrupt Flag Register; Pwg2 Interrupt Enable Register; Clg System Clock Control Register - Epson S1C17W14 Technical Manual

PWG2 Timing Control Register

Register name Bit
PWGTIM 15–8 –
7–2 –
1–0 DCCCLK[1:0]
Bits 15–2 Reserved
Bits 1–0 DCCCLK[1:0]
These bits set the charge pump operating clock (select an OSC1 clock division ratio).

PWG2 Interrupt Flag Register

Register name Bit
PWGINTF 15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0 MODCMPIF
This bit indicates the PWG2 mode transition completion interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective

PWG2 Interrupt Enable Register

Register name Bit
PWGINTE 15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0 MODCMPIE
These bits enable the PWG2 mode transition completion interrupt.
1 (R/W): Enable interrupt
0 (R/W): Disable interrupt

CLG System Clock Control Register

Register name Bit
CLGSCLK 15
14
13–12 WUPDIV[1:0]
11–10 –
9–8 WUPSRC[1:0]
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
S1C17W14/W16 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x00
0x00
0x0
Table 2.6.2 Charge Pump Operating Clock Setting
PWGTIM.DCCCLK[1:0] bits
0x3
0x2
0x1
0x0
Bit name Initial
0x00
0x00
MODCMPIF 0
Bit name Initial
0x00
0x00
MODCMPIE 0
Bit name Initial
WUPMD 0
– 0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset R/W
– R –
– R
H0 R/WP
OSC1 division ratio
1/256
1/128
1/64
1/32
Reset R/W
– R –
– R
H0 R/W
Reset R/W
– R –
– R
H0 R/W
Reset R/W
H0 R/WP –
– R
H0 R/WP
– R
H0 R/WP
– R
H0 R/WP
– R
H0 R/WP
Remarks
Remarks
Remarks
Remarks
2-17