Dma Controller (Dmac) - Epson S1C31D01 Software Manual

Cmos 32-bit single chip microcontroller peripheral circuit sample software manual
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DMA Controller (DMAC)

3.2
The DMAC module is used for data transfers between memory and peripheral devices.
This example shows:
Using DMAC in a basic memory-to-memory data transfer
Using DMAC from memory to a peripheral data transfer
Using DMAC from a peripheral to memory data transfer
Using DMAC concurrent peripheral to memory and memory to peripheral data transfer
For more examples of using DMACC for transfers see QSPI_DMA Example code.
Hardware Setup
To demonstrate UART DMA transfer, connect UART on the S5U1C31D01T1 evaluation board to PC by a USB
Adapter for UART. (see Figure 2.2.2.1, Figure 2.2.2.2)
Operations
Example 1: Memory to Memory DMA transfer
DMAC Channel 0 is configured to transfer the contents of a data buffer stored in RAM to the reception
buffer also in RAM. Access size is Byte.
DMAC Channel 1 is configured to transfer the contents of a data buffer stored in RAM to the reception
buffer in RAM. Access size is Half Word.
DMAC Channel 2 is configured to transfer the contents of a data buffer stored in RAM to the reception
buffer in RAM. Access size is Word.
The start of transfer is triggered by software.
In this example:
1.
The DMAC interrupts in NVIC are not enabled.
2.
DMAC Channel transfer is enabled.
3.
Source and destination addresses incrementing is enabled.
4.
The transfer is started by setting the Software Request register bits.
5.
At the end of the transfer, a Transfer Completion interrupt flag is generated.
6.
Once interrupt flag is generated, the "number of transfers" is read which must be equal to 0.
7.
The Transfer Complete Interrupt flag is then cleared.
8.
A comparison between the source and destination buffers is done to check that all data have been
correctly transferred.
Example 2: Memory to Peripheral DMA transfer
DMAC Channel 0 is configured to transfer data from a buffer stored in RAM memory to SNDA data
register.
SNDA is configured to play melody.
The start of transfer is triggered by SNDA.
In this example:
1.
The DMAC interrupts in NVIC are not enabled.
2.
DMAC Channel transfer is enabled.
3.
DMAC Channel filtering is disabled for the selected DMAC Channel.
4.
Source address incrementing is enabled.
5.
Destination address incrementing is disabled.
30
Seiko Epson Corporation
S1C31D01 Peripheral Circuit Sample
Software Manual (Rev.3.00)

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