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(5) Generating repeated start condition
The procedure is the same as that of data transmission in I
Clock stretch function
During transmitting/receiving data, the slave device may issue a wait request to the master device by pulling
down the SCL line to low until the slave device becomes ready to transmit/receive the subsequent data. The
master device enters a standby state until the wait request is canceled (the SCL line goes high).
This I
2
C controller supports this clock stretch function. When a clock stretch condition is detected after a slave
address or data has been sent/received, this module enters a waiting status and it does not start operating even if
it accepts a trigger for data transfer until the clock stretch status is canceled. IMBSY is maintained at 1 until the
triggered operation has completed including a waiting status.
USI_CK pin (master output)
USI_CK pin (slave output)
Control method in I
2
Data transfer in I
C slave mode is controlled using ISTGMOD[2:0]/USI_ISTG register and ISTG/USI_ISTG
2
register. Select an I
2
C slave operation using ISTGMOD[2:0] and write 1 to ISTG as the trigger. The I
troller controls the I
C bus to generate the specified operating status.
2
Writing 1 to ISTG sets ISBSY/USI_ISIF register to 1 indicating that the I
When the specified operation has finished, ISBSY is reset to 0. At the same time, the interrupt flag (ISIF/USI_
ISIF register) is also set to 1. After an interrupt occurs, read the status bits (ISSTA[2:0]/USI_ISIF register) to
check the operation finished. Then, clear ISIF by writing 1. This also automatically reset ISSTA[2:0] to 0x0.
S1C33L26 TECHNICAL MANUAL
Clock stretch
Figure 18.
C slave mode
Table 18.
5.3.3 Trigger List in I
ISTGMOD[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Table 18.
5.3.4 I
ISSTA[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko Epson Corporation
18 UNIVERSAL SERIAL INTERFACE (USI)
2
C master mode.
5.3.10 Clock Stretch
2
C Slave Mode
Trigger
Reserved
ACK/NAK reception
NAK transmission
ACK transmission
Data reception/stop condition detection
Data transmission
Reserved
Wait for start condition
2
C Slave Status Bits
Status
Reserved
NAK has been received.
ACK has been received.
ACK or NAK has been sent.
End of receive data.
End of transmit data.
Stop condition has been detected.
Start condition has been detected.
Clock stretch
(Default: 0x0)
C controller is busy (operating).
2
(Default: 0x0)
2
C con-
18-15
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