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• Supports reset requests from multiple reset sources.
- #RESET pin
- POR and BOR
- Key-entry reset
- Watchdog timer reset
- Supply voltage detector reset
- Peripheral circuit software reset (supports some peripheral circuits only)
• The CPU registers and peripheral circuit control bits will be reset with an appropriate initialization condition ac-
cording to changes in status.
Figure 2.2.1.1 shows the SRC configuration.
#RESET
Key-entry reset
Watchdog timer reset
Supply voltage detector reset
Software reset 0
Software reset n
2.2.2
Input Pin
Table 2.2.2.1 shows the SRC pin.
Pin name
#RESET
The #RESET pin is connected to the noise filter that removes pulses not conforming to the requirements. An inter-
nal pull-up resistor is connected to the #RESET pin, so the pin can be left open. For the #RESET pin characteris-
tics, refer to "#RESET pin characteristics" in the "Electrical Characteristics" chapter.
2.2.3
Reset Sources
The reset source refers to causes that request system initialization. The following shows the reset sources.
#RESET pin
Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request.
POR and BOR
POR (Power On Reset) issues a reset request when the rise of V
a reset request when a certain V
system will be reset properly when the power is turned on and the supply voltage is out of the operating voltage
range. Figure 2.2.3.1 shows an example of POR and BOR internal reset operation according to variations in V
S1C17F13 TeChniCal Manual
(Rev. 1.0)
SRC
V
DD
Reset request
signals
Noise filter
V
POR
SS
BOR
Figure 2.
2.1.1 SRC Configuration
Table 2.
I/O
Initial status
I
I (Pull-up)
voltage level is detected. Reset requests from these circuits ensure that the
DD
Seiko epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Clock generator
Boot clock
OSC3BCLK
Internal reset signals
(Reset group)
SYSRST_H0
Reset hold
circuit
SYSRST_H1
SYSRST_S0_0
Reset
decoder
SYSRST_S0_n
2.2.1 SRC Pin
Reset input
is detected. BOR (Brownout Reset) issues
DD
To CPU and peripheral circuits
To CPU and peripheral circuits
To peripheral circuit 0
To peripheral circuit n
Function
.
DD
2-3
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