Pacific Power Source ADF Series Operation Manual page 148

• Even if TTL input is used, there can be a phase shift that depends on the output load
because of the finite bandwidth of the output inverter stages. This is particularly
visible at higher frequencies. At 50Hz or 60Hz, the phase shift will be pretty small.
Note: When the sync input is enabled, the ADF frequency set point must be set to a value
similar to the external sync signal. This minimizes the synchronization time and
improves the stability of the generated frequency.
After the sync input is activated, or the external signal frequency/phase is changed, the Sync
circuit's Phase Lock Loop (PLL) requires a short time to "lock" to the external source. The
ADF reports the status of the PLL in the external interfaces (front panel and webpage) by
showing a "Synced" or "Unsynced" message in the status bars. (See section 0 for details).
The status can also be queried with the SCPI command "SOURce:SYNChronize:STATe?".
The sync circuit is able to synchronize to any signal with a frequency if F
where F
SETPOINT
10Hz)
The following specifications apply to the phase sync input at the DB25 port:
Input Voltage
Impedance
Frequency Range
Edge Triggered

Entire Contents Copyright 2018 by Pacific Power Source, Inc. (PPS) • All Rights Reserved • No reproduction without written authorization from PPS.
ADF Series Power Source Operation Manual
is the normal frequency set point and F
Logic Low Vin < 0.4 V
Log High Vin > 2.0 V
10 kΩ
15 Hz – 1200 Hz
Rising edge
Figure 7-4: External Sync Input Pulses
ADF SERIES™ OPERATION MANUAL
Rear Panel, Connectors and Protection
SECTION 7:
is a configurable value (default is
RANGE
+/- F ,
SETPOINT RANGE
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