Test References - Keysight U7233A Testing Notes

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9
10 After obtaining the Edge number for the respective signal, begin the tDQSS measurement bit by
11 Continue the measurement until the last bit (for instance, until a tristate happens, which
12 DQS-Clock timing measurement compares the rising edge (DQS crossing against clock crossing)
13 Within the data burst, measure each bit, for instance the rising edge of the DQS-Clock. Capture
14 Once all bits are validated, assign marker A for the clock signal while marker B for the data signal,
15 Measure delta of marker A and marker B and this will be the test result.
16 Compare the test result against the compliance test limit.

Test References

See Table 11 - Electrical Characteristics and AC Timing, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
If you have selected the CS option, skip the next step and go to step 9.
Search for the DQS preamble towards the left from the point where the Read cycle was previously
captured. The For loops, TEdge and Delta Time are used to search the preamble.
Once the preamble is located, call the "BinaryEdgeNormal" function to obtain the Edge number
of clock rising edge and strobe rising edge. This Edge number will be used for TEdge
measurement, in order to locate the points of interest on specific signal.
bit in the Write data burst, beginning from the 1st bit of the Write cycle. Begin at the 1st bit of the
read cycle, from the Write preamble.
indicates the end of a data burst for the respective Write cycle).
OR the falling edge (DQS crossing against Vih_dc of the DQ signal, for instance, end of valid DQ
hold time).
the worst case data each time a new value is measured.
for the worst case bit.
Data Strobe Timing (DST) Tests 7
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