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3
Single-Ended Signals AC Input Parameters Tests
V
Test Method of Implementation
IL(DC)
V
IL(DC)
level voltage value of the test signal within a valid sampling window is within the conformance limits
of the V
The default value of V
change this value.
Table 14
Speed
V
V
Figure 11
Signals of Interest
Based on the test definition (Write cycle only):
•
•
•
•
•
50
- Maximum DC Input Logic Low. The purpose of this test is to verify that the maximum low
value specified in the JEDEC Standard JESD79E.
IL(DC)
and V
REF
The defaul t value of V
REF
DDR 200, 266, 333
2.50 V
DDQ
1.25 V
REF
V
Test - Maximum DC Input Logic Low in Infiniium oscilloscope
IL(DC)
Data Signal
Data Strobe Signal OR
Address Signal OR
Control Signal OR
Data Mask Control Signals
is as shown in
Table
14. However, users have the flexibility to
DDQ
and V
DDQ
DDR 400
2.60 V
1.30 V
DDR1 Compliance Testing Methods of Implementation
Low Power
1.80 V
0.90 V
.
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