Test References - Keysight U7233A Testing Notes

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10 After obtaining the Edge number for the respective signal, begin the tQH measurement bit by bit
11 Begin at the 1st bit of the Read cycle, from the Read preamble. Continue the measurement until
12 DQS-DQ timing measurement compares the rising edge (DQS crossing against Vil_dc of the DQ
13 Within the data burst, measure each bit, for instance the rising and falling edge of the DQS-DQ.
14 Once all bits are validated, assign marker A for the lock signal while marker B for the data signal,
15 Measure delta of marker A and marker B and this will be the test result.
16 Compare the test result against the compliance test limit.

Test References

See Table 11 - Electrical Characteristics and AC Timing, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Chip Select (CS) option is only applicable if the user has selected "Yes" for the Verify Selected
Rank Only option in the Configuration page. It uses the CS-DQS for signal separation. Else, by
default, the DQS-DQ is used for signal separation.
Use the InfiniiScan feature with the Setup time and Hold time to find and capture the Read cycle.
If you have selected the CS option, skip the next step and go to step 9.
Search for the DQS preamble towards the left from the point where the Read cycle was previously
captured. The For loops, TEdge and Delta Time are used to search the preamble.
Once the preamble is located, call the "BinaryEdgeNormal" function to obtain the Edge number
of the DQS and DQ signal. This Edge number will be used for the TEdge measurement, in order to
locate the points of interest on specific signal.
in Read Data Burst, beginning from the 1st bit of the Read cycle.
the last bit (for instance, until a tristate happens, which indicates the end of a data burst for the
respective Read cycle).
signal, for instance, end of valid DQ hold time) OR the falling edge (DQS crossing against Vih_dc
of the DQ signal, for instance, end of valid DQ hold time).
Capture the worst case data each time a new value is measured.
for the Worst Case bit.
Data Strobe Timing (DST) Tests 7
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