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8
Clock Timing (CT) Tests
AC Characteristics - Parameter
DQ output access time from CK/CK
Table 50
AC Timing Variations for DDR 333, DDR 266 & DDR 200 Devices
Parameter
DDR 333B
Min
Max
tAC
-0.7
0.7
Pass Condition
The measured time interval between the data access output and the rising edge of the clock should
be within the specification limits.
Measurement Algorithm
1
2
3
4
5
6
7
8
9
10 After obtaining the Edge# for the respective signal, begin the tAC measurement bit by bit in Read
11 Continue the measurement until last bit (for example, until a tristate happens, which indicates
12 DQ-Clock timing measurement compares the Rising Edge (Vih_ac OR Vil_dc against clock
13 Within the data burst, measure each bit, for instance rising and falling edge of DQ-Clock. Capture
14 Once all bits are validated, assign marker A for clock signal while marker B for data signal, for the
15 Measure delta of marker A and marker B and this will be the test result.
16 Compare the test result against the compliance test limit.
122
Symbol
DDR 400A (2.5-3-3)
Min
tAC
-0.7
DDR 266A
Min
Max
-0.75
0.75
Obtain the parameters and settings from the Configuration page.
Pre-condition the scope setting. Verify the actual DUT speed against user speed selection at the
Setup page.
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Chip Select (CS) option is only applicable if the user has selected "Yes" for the Verify Selected
Rank Only option in the Configuration page. It uses the CS-DQS for signal separation. Else, by
default, the DQS-DQ is used for signal separation.Search for the DQS pre-amble towards the left
from the point where the Read Cycle was previously captured. The For loops, TEdge and
DeltaTime are used to search the pre-amble.
Use the InfiniiScan feature with the Setup time and Hold time to find and capture the Read cycle.
If you have selected the CS option, skip the next step and go to step 9.
Search for the DQS preamble towards the left from the point where the Read cycle was previously
captured. The For loops, TEdge and Delta Time are used to search the preamble.
Once the preamble is located, call the "BinaryEdgeNormal" function to obtain the Edge number.
This Edge number will be used to locate the point of interest on the specific signal.
Data Burst. Begin at the 1st bit of the Read cycle, from the Read pre-amble.
the end of a Data Burst for the respective Read Cycle).
crossing) OR the Falling Edge (Vil_ac OR Vih_dc against clock crossing).
the worst case data each time a new value is measured.
Worst Case bit.
DDR 400B (3-3-3)
Max
Min
Max
+0.7
-0.7
+0.7
DDR 266B
DDR 200
Min
Max
Min
-0.75
0.75
-0.8
DDR1 Compliance Testing Methods of Implementation
DDR 400C (3-4-4)
Units
Min
Max
-0.7
+0.7
ns
DDR 200B
Max
Min
Max
0.8
-0.8
0.8
Notes
Units
ns
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