Average Low Pulse Wid Th - Tcl(Avg) - Test Method Of Implementation; Average Low Pulse Width - Tcl(Avg) - Test Method Of Implementation; Signals Of Interest; Test Definition Notes From The Specification - Keysight U7233A Testing Notes

Average Low Pulse Width - tCL(avg) - Test Method of Implementation

The purpose of this test is to measure the average duty cycle of all the negative pulse widths within a
window of 200 consecutive cycles.

Signals of Interest

Based on the test definition:
•
Signals required to perform the test on the oscilloscope:
•

Test Definition Notes from the Specification.

Table 56 Electrical Characteristics and AC Timing
AC Characteristics Parameter
CK low-level width
AC Characteristics Parameter
CK low-level width

Pass Condition

The tCL measurement value should be within the conformance limits as specified in the JEDEC
Standard JESD79E.

Measurement Algorithm

Example input test signal: Frequency: 1 KHz, Number of cycles acquired: 202.
1
2
3
4

Test References

See Table 11 - Electrical Characteristics and AC Timing, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
Clock Signal
Clock Signal - CK is required to perform pre-test to verify the DUT speed against user's speed
grade selection
Symbol
Min
tCL 0.45
Symbol DDR 400A (2.5-3-3)
Min
tCL 0.45
Measure the sliding "window" of 200 cycles.
Measure the width of the low pulses (1-200, 2-201 and 3-202) and determine the average value
for this window.
Check the total 3 results for the smallest and largest values (worst case values).
Compare results against the compliance test limits.
DDR 333 DDR 266
Max Min Max
0.55 0.45 0.55
DDR 400B (3-3-3)
Max Min Max
0.55 0.45 0.55
Clock Timing (CT) Tests
DDR 200 Units
Min Max
0.45 0.55 tCK
DDR 400C (3-4-4) Units
Min Max
0.45 0.55 tCK
8
Notes
Notes
131