Test References - Keysight U7233A Testing Notes

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6
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9
10 Define the histogram window in order to obtain the Min and Max voltage for the DQS postamble
11 Once all points are obtained, proceed with the trigonometry calculation to find the point where
12 Assign marker A for the DQS signal crossing point while marker B for the data strobe signal start
13 Measure delta of marker A and marker B and this will be the test result.
14 Compare the test result against the compliance test limit.

Test References

See Table 11 - Electrical Characteristics and AC Timing, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
Chip Select (CS) option is only applicable if the user has selected "Yes" for the Verify Selected
Rank Only option in the Configuration page. It uses the CS-DQS for signal separation. Else, by
default, the DQS-DQ is used for signal separation.
Use the InfiniiScan feature with the Setup time and Hold time to find and capture the Read cycle.
If you have selected the CS option, skip the next step and go to step 9.
Search for the DQS postamble towards the right from the point where the Write cycle was
previously captured. The For loops, TEdge and Delta Time are used to search the postamble.
Once the postamble is located, call the "BinarySearchNormal" function to locate the last DQS
crossing point or reference point.
signal and it will be used for the threshold setup for the trigonometry calculation later.
the DQS starts to transit from high/low to the time when it starts to turn off the driver low (for
instance, end of burst or postamble).
to turn off driver.
Data Strobe Timing (DST) Tests 7
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