Implementation; Signals Of Interest; Test Definition Notes From The Specification; Pass Condition - Keysight U7233A Testing Notes

7 Data Strobe Timing (DST) Tests

tDQSQ, DQS-DQ Skew for DQS and Associated DQ Signals - Test Method of Implementation

The purpose of this test is to verify that the time interval from the data strobe output (DQS rising and
falling edge) access time to the associated data (DQ rising and falling) signal is within the
conformance limit as specified in the JEDEC Standard JESD79E.

Signals of Interest

Based on the test definition (Read cycle only):
•
•
Signals required to perform the test on the oscilloscope:
•
•
•
Optional signal required to separate the signals for the different Ranks:
•

Test Definition Notes from the Specification

Table 37 Electrical Characteristics and AC Timing
AC Characteristics Parameter
DQS-DQ Skew (for DQS &
associated DQ signals)
AC Characteristics Parameter
DQS-DQ Skew (for DQS &
associated DQ signals)
NOTE 26: tDQSQ Consists of data pin skew and output pattern effects, and p=channel to n-channel
variation of the output drivers for any given cycle.

PASS Condition

The measured time interval between the data strobe and the associated data signal should be within
specification limit.

Measurement Algorithm

1
2
3
94
Data Signal (DQ as Pin Under Test Signal)
Data Strobe Signal (DQS as Supporting Signal)
Data Signal (DQ as Pin Under Test Signal)
Data Strobe Signal (DQS as Supporting Signal)
Clock Signal (CK as Reference Signal)
Chip Select Signal (CS as additional signal, which requires an additional channel)
Symbol
TSOP Pkg tDQSQ
BGA Pkg tDQSQ
Symbol
TSOP Pkg tDQSQ
BGA Pkg tDQSQ
Obtain the parameters and settings from the Configuration page.
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
DDR 333 DDR 266
Min Max Min Max
+0.45 +0.5
+0.4 +0.5
DDR 400A DDR 400B (3-3-3)
(2.5-3-3)
Min Max Min Max
+0.4 +0.4
+0.4 +0.4
DDR1 Compliance Testing Methods of Implementation
DDR 200 Units Notes
Min Max
+0.6 ns 26
+0.6 ns 26
DDR 400C (3-4-4) Units Notes
Min Max
+0.4 ns 26
+0.4 ns 26