Keysight U7233A Testing Notes page 144

Ddr1 compliance test application
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10
Command and Address Timing (CAT) Tests
9
Table 60
Configuration Option
Stop on error
Signal Threshold setting by percentage
VDD
VDDQ
Vref
Vih(DC)
Vih(AC)
Vil(DC)
Vil(AC)
Timing Tests
Total Bit Display
Total Measurement Required
Option
Pin Under Test, PUT
144
Follow the DDR1 Test application's task flow to set up the configuration options (see
the tests and view the tests results.
Test Configuration Options
Description
Enabling this error message will allow error message to prompt whenever criteria is not
met. Disabling this option will allow the system to bypass all the error messages that
could occur and continue to the next test. This option is suitable for long hours multiple
trial.
This option allow user to define the Upper and Lower threshold of the signal by
percentage.
Input supply voltage value.
Input supply voltage for data output.
Input reference voltage value.
Input voltage high value (direct current).
Input voltage high value (alternating current).
Input voltage low value (direct current).
Input voltage low value (alternating current).
Allows user to select the number of data bits to be displayed at the end of the test.
Selecting more bits gives a better view of the entire burst of signals.
To perform the total number of measurement based on user selection.
Identifies the signal used for testing.
Signal used for testing.
DDR1 Compliance Testing Methods of Implementation
Table
60), run

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