Twpre, Write Preamble - Test Method Of Implementation; Signals Of Interest; Test Definition Notes From The Specification - Keysight U7233A Testing Notes

7 Data Strobe Timing (DST) Tests

tWPRE, Write Preamble - Test Method of Implementation

The purpose of this test is to verify that the time when the DQS starts to drive low (preamble
behavior) to the first DQS signal crossing for the Write cycle, is within the conformance limit as
specified in the JEDEC Standard JESD79E.
Figure 35

Signals of Interest

Based on the test definition (Write cycle only):
•
Signals required to perform the test on the oscilloscope:
•
•
•
Optional signal required to separate the signals for the different Ranks:
•

Test Definition Notes from the Specification

Table 45 Electrical Characteristics and AC Timing
AC Characteristics Parameter
Write preamble
110
tWPRE in Infiniium oscilloscope
Data Strobe Signal (DQS as Pin Under Test Signal)
Data Strobe Signal (DQS as Pin Under Test Signal)
Data Signal (DQ as Supporting Signal)
Clock Signal (CK as Reference Signal)
Chip Select Signal (CS as additional signal, which requires an additional channel)
Symbol DDR 333
Min
tWPRE 0.25
DDR 266
Max Min
0.25
DDR1 Compliance Testing Methods of Implementation
DDR 200
Max Min
0.25
Units
Max
tCK