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10
Command and Address Timing (CAT) Tests
Measurement Algorithm
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Test References
See Table 11 - Electrical and AC Timing, in the JEDEC Standard JESD79E.
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Obtain the parameters and settings from the Configuration page.
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the CK-DQS.
tIH measurement will compare the rising edge (address/control rising e.g. Vih_dc against
associated clock crossing) OR falling edge (address/control falling e.g. Vil_dc against associated
clock crossing).
Assign marker A for the clock signal while marker B for the data signal, for the final measurement
result.
Measure delta of marker A and marker B and this will be the test result.
Compare the test result against the compliance test limit.
DDR1 Compliance Testing Methods of Implementation
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