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9
Data Mask Timing (DMT) Tests
9
Table 57
Configuration Option
Stop on error
Signal Threshold setting by percentage
VDD
VDDQ
Vref
Vih(DC)
Vih(AC)
Vil(DC)
Vil(AC)
Timing Tests
Total Bit Display
Verify Selected Rank Only?
Channel (1,2,3)
Pin Under Test, PUT
136
Follow the DDR1 Test Application's task flow to set up the configuration options (see
run the tests and view the tests results.
Test Configuration Options
Description
Enabling this error message will allow error message to prompt whenever criteria is not
met. Disabling this option will allow the system to bypass all the error messages that could
occur and continue to the next test. This option is suitable for long hours multiple trial.
This option allow user to define the Upper and Lower threshold of the signal by
percentage.
Input supply voltage value.
Input supply voltage for data output.
Input reference voltage value.
Input voltage high value (direct current).
Input voltage high value (alternating current).
Input voltage low value (direct current).
Input voltage low value (alternating current).
Allows user to select the number of data bits to be displayed at the end of the test.
Selecting more bits gives a better view of the entire burst of signals.
If you choose Yes, you require an additional channel for the Chip Select (CS). Measurement
will only be done on the selected rank based on the Chip Select signal connected to the
oscilloscope.
Signal connected to the specific channel.
Signal used for testing.
DDR1 Compliance Testing Methods of Implementation
Table
57),
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