Keysight U7233A Testing Notes page 195

Ddr1 compliance test application
Table of Contents

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Index
A
AC Differential Input Cross Point
Voltage,
78
AC Differential Input Voltage,
Address and Control Input Hold
Time,
147
Address and Control Input Setup
Time,
145
Average Clock Period,
128
Average High Pulse Width,
Average Low Pulse Width,
B
BNC shorting cap,
170
BNC to SMA male adapter,
C
calibrating the oscilloscope,
calibration cable,
170
Clock Period Jitter,
154
Clock Timing (CT) Tests,
117
Clock to Clock Period Jitter,
computer motherboard system,
configure,
28
connect,
28
Cumulative Error,
156
D
Data Mask Timing (DMT) Tests,
Data Strobe Timing (DST) Tests,
differential browser,
6
differential solder-in probe head, 6,
185
DQ and DM Input Hold Time,
DQ and DM Input Setup Time,
DQ Low-Impedance Time from
CK/CK#,
91
DQ Out High Impedance Time From
CK/CK#, 85,
87
DQ/DQS Output Hold Time From
DQS,
96
DQS Falling Edge Hold Time from
CK,
106
DQS Falling Edge to CK Setup
Time,
104
DQS Input High Pulse Width,
DQS Input Low Pulse Width,
DDR1 Compliance Testing Methods of Implementation
DQS Latching Transition to Associated
Clock Edge,
DQS Low-Impedance Time from
CK/CK#,
DQS Output Access Time from CK/CK
75
#,
124
DQS-DQ Skew for DQS and Associated
DQ Signals,
E
131
131
error messages,
H
Half Period Jitter,
170
High State Ringing Tests,
HTML report,
I
169
in this book,
InfiniiScan software license,
Input Signal Minimum Slew Rate
155
(Falling),
6
Input Signal Minimum Slew Rate
(Rising),
internal calibration,
K
keyboard, 6,
133
81
L
license key, installing,
Low State Ringing Tests,
139
137
M
Maximum AC Input Logic High,
Maximum AC Output Logic High,
Maximum DC Input Logic Low,
Minimum AC Input Logic Low,
Minimum AC Output Logic Low,
Minimum DC Input Logic High,
mouse, 6,
170
100
O
102
over/undershoot tests,
98
89
94
187
157
164
28
7
6
38
35
171
170
23
166
41
57
50
47
59
44
61
P
precision 3.5 mm BNC to SMA male
adapter,
170
probe calibration,
175
Probing for Advanced Debug Mode
High-Low State Ringing Tests,
Probing for Clock Timing Tests,
Probing for Command and Address
Timing Tests,
142
Probing for Data Mask Timing
Tests,
134
Probing for Data Strobe Timing
Tests,
82
Probing for Differential Signals AC
Input Parameters Tests,
Probing for Measurement Clock
Tests,
150
Probing for Overshoot/Undershoot
Tests,
62
Probing for Single-Ended Signals AC
Input Parameters Tests,
Probing for Single-Ended Signals AC
Output Parameters Tests,
R
RAM reliability test software,
Read Postamble,
114
Read Preamble,
112
report,
28
required equipment and software,
required equipment for calibration,
results,
28
run tests,
28
S
select tests,
28
SlewF,
38
SlewR,
35
start the DDR1 Compliance Test
Application,
27
T
tAC,
121
tCH(avg),
130
tCK(avg),
128
tCL(avg),
131
tDH(base),
139
tDQSCK,
121
160
118
72
32
54
6
6
170
195

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