Table of Contents
Advertisement
7
Data Strobe Timing (DST) Tests
tRPRE, Read Preamble - Test Method of Implementation
The purpose of this test is to verify that the time when the DQS start driving low (*preamble behavior)
to the first DQS signal crossing for the Read cycle must be within the conformance limit as specified
in the JEDEC Standard JESD79E.
Signals of Interest
Based on the test definition (Read cycle only):
•
Signals required to perform the test on the oscilloscope:
•
•
•
Optional signal required to separate the signals for the different Ranks:
•
Test Definition Notes from the Specification
Table 46
Electrical Characteristics and AC Timing
AC Characteristics Parameter
Read preamble
AC Characteristics Parameter
Read preamble
NOTE 28: Optional CAS Latency, 1.5, is only defined for DDR 200 speed grade
NOTE 33: tRPST end; point adn tRPRE begin point are not referenced to a specific voltage level but
specify when the device output is no longer driving (tRPST), or begins driving (tRPRE).
PASS Condition
The measured time interval of the point where the DQS starts to transit from tristate (high impedance
state to low state) to the DQS signal crossing point for the Read cycle should be within the
specification limit.
112
Data Strobe Signal (DQS as Pin Under Test Signal)
Data Strobe Signal (DQS as Pin Under Test Signal)
Data Signal (DQ as Supporting Signal)
Clock Signal (CK as Reference Signal)
Chip Select Signal (CS as additional signal, which requires additional channel)
CL = 2.5
CL = 2.0
CL = 2.5
CL = 3
CL = 2.5
CL = 2.0
CL = 1.5
Symbol
DDR 333
Min
Max
Min
tRPRE
0.9
1.1
0.9
0.9
1.1
0.9
NA
NA
NA
Symbol
DDR 400A
(2.5-3-3)
Min
Max
Min
tRPRE
0.9
1.1
0.9
0.9
1.1
0.9
0.9
1.1
0.9
NA
NA
NA
DDR1 Compliance Testing Methods of Implementation
DDR 266
DDR 200
Max
Min
Max
1.1
0.9
1.1
1.1
0.9
1.1
NA
-
1.1
DDR 400B
DDR 400C
(3-3-3)
(3-4-4)
Max
Min
Max
1.1
0.9
1.1
1.1
0.9
1.1
1.1
0.9
1.1
NA
NA
NA
Units
Notes
tCK
28, 33
tCK
28, 33
tCK
28, 33
Units
Notes
tCK
28, 33
tCK
28, 33
tCK
28, 33
Advertisement
Table of Contents
