Test Definition Notes From The Specification; Pass Condition; Measurement Algorithm; Test References - Keysight U7233A Testing Notes

Test Definition Notes from the Specification

Table 29 AC Operating Cond itions
Parameter
Input Differential Voltage, CK and CK# inputs
NOTE 9: V
CK#.

PASS Condition

The calculated magnitude of the differential voltage for the test signals pair can be within the
conformance limits of the V

Measurement Algorithm

1
2
3
4
5
6
7
8

Test References

See Table 7 - AC Operating Conditions, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
is the magnitude of the difference between the input level on CK and the input level on
ID
ID(AC)
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Obtain sample or acquire signal data and perform signal conditioning to maximize the screen
resolution (vertical scale adjustment).
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Obtain sample or acquire data waveforms, for example CK+ and CK-.
Use histogram function (mode value) to find the nominal high level value for CK+ and nominal
low level value for CK-.
Subtract the CK- low level value from the CK+ high level value.
Compare the test results against the compliance test limits.
Differential Signals AC Input Parameters Tests
Symbol Min
V 0.7
ID(AC)
value.
Max Units
V + 0.6 V
DDQ
6
Notes
9
77