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Signals of Interest
Based on the test definition (Write cycle only):
•
Signals required to perform the test on the oscilloscope:
•
Test Definition Notes from the Specification
Table 31
AC Operating Cond itions
Parameter
Input Differential Voltage, CK and CK# inputs
NOTE 10: The value of V
input level on CK#.
PASS Condition
The measured crossing point value for the differential test signals pair can be within the conformance
limits of V
Measurement Algorithm
1
2
3
4
5
6
7
8
9
Test References
See Table 7 - AC Operating Conditions, in the JEDEC Standard JESD79E.
DDR1 Compliance Testing Methods of Implementation
Clock Signal
Clock Signal - CK is required to perform pre-test to verify the DUT speed against user's speed
grade selection
Symbol
V
IX(AC)
is the magnitude of the difference between the input level on CK and the
ID
value.
IX(AC)
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Obtain sample or acquire signal data and perform signal conditioning to maximize the screen
resolution (vertical scale adjustment).
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Obtain sample or acquire data waveforms, for example CK+ and CK-.
Generate the differential waveform from two source input.
Get the timestamp of voltage value = 0 V level (crossing point).
Get the actual crossing value using the obtained timestamp.
Compare the test results against the compliance test limits.
Differential Signals AC Input Parameters Tests
Min
Max
0.5 * V
- 0.2
0.5 * V
+ 0.2
DDQ
DDQ
6
Units
Notes
V
10
79
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