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7
Data Strobe Timing (DST) Tests
•
•
•
Optional signal required to separate the signals for the different Ranks:
•
Test Definition Notes from the Specification
Table 36
Electrical Characteristics and AC Timing
AC Characteristics Parameter
DQ & DQS low-impedance time from CK/CK
AC Characteristics Parameter
DQ & DQS low-impedance time from CK/CK
NOTE 15: tHZ and tLZ transitions occurs in the same access time as valid data transitions. These
parameters are referenced to a specific voltage level which specifies when the device output is no
longer driving (tHZ), or begin driving (tLZ).
device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different
voltages. The actual voltage measurement points are not critical as long as the calculation is
consistent.
PASS Condition
The measured time interval from the point where the DQ starts to transit from high impedance to the
moment when it starts to drive high/low (high impedance state to high/low state), to the clock signal
crossing point, should be within the specification limit.
Measurement Algorithm
1
2
3
4
5
6
7
8
9
92
Data Signal (DQ as Pin Under Test Signal)
Data Strobe Signal (DQS as Supporting Signal)
Clock Signal (CK as Reference Signal)
Chip Select Signal (CS as additional signal, which requires an additional channel)
Symbol
Min
tLZ
-0.70
Symbol
DDR 400A (2.5-3-3)
Min
tLZ
-0.70
Obtain the parameters and settings from the Configuration page.
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Chip Select (CS) option is only applicable if the user has selected "Yes" for the Verify Selected
Rank Only option in the Configuration page. It uses the CS-DQS for signal separation. Else, by
default, the DQS-DQ is used for signal separation.
Use the InfiniiScan feature with the Setup time and Hold time to find and capture the Read cycle.
If you have selected the CS option, skip the next step and go to step 9.
Search for the DQS preamble towards the left from the point where the Read cycle was previously
captured. The For loops, TEdge and Delta Time are used to search the preamble.
Once the preamble is located, call the "BinaryEdgeNormal" function, using the Clock as the
reference to define the Histogram Window for the DQ signal.
DDR 333
DDR 266
Max
Min
Max
+0.70
-0.75
+0.75
DDR 400B (3-3-3)
Max
Min
Max
+0.70
-0.70
+0.70
Figure 33
shows a method to calculate the point when
DDR1 Compliance Testing Methods of Implementation
DDR 200
Units
Min
Max
-0.8
+0.8
ns
DDR 400C (3-4-4)
Units
Min
Max
-0.70
+0.70
ns
Notes
15
Notes
15
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