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V
Test Method of Implementation
IL(AC)
V
IL
V
IL(AC)
voltage value of the test signal is lower than the conformance maximum limit of the V
specified in the JEDEC Standard JESD79E. For low power devices, the measured value must fall in
between the conformance limits.
The default value of V
change this value.
Table 11
Speed
V
V
Figure 10
Signals of Interest
Based on the test definition (Write cycle only):
•
•
•
DDR1 Compliance Testing Methods of Implementation
AC Input Logic Low High Test can be divided into two sub tests: V
- Minimum AC Input Logic Low. The purpose of this test is to verify that the minimum low level
and V
REF
The defaul t value of V
REF
DDR 200, 266, 333
2.50 V
DDQ
1.25 V
REF
V
Test - Minimum AC Input Logic Low in Infiniium oscilloscope
IL(AC)
Data Signal
Data Strobe Signal OR
Control Signal OR
Single-Ended Signals AC Input Parameters Tests
is as shown in
Table
11. However, users have the flexibility to
DDQ
and V
DDQ
DDR 400
2.60 V
1.30 V
test and V
test.
IL(AC)
IL(DC)
value
IL(AC)
Low Power
1.80 V
0.90 V
.
3
47
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