Tlz(Dq), Dq Low-Impedance Time From Ck/Ck# - Test Method Of Implementation; Signals Of Interest - Keysight U7233A Testing Notes

Ddr1 compliance test application
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tLZ(DQ), DQ Low-Impedance Time from CK/CK# - Test Method of Implementation

The purpose of this test is to verify that the time when the DQ starts driving (from high impedance
state to high/low state), to the clock signal crossing, is within the conformance limit as specified in
the JEDEC Standard JESD79E.
Figure 33
Figure 34

Signals of Interest

Based on the test definition (Read cycle only):
Signals required to perform the test on the oscilloscope:
DDR1 Compliance Testing Methods of Implementation
Method for Calculating Transitions and Endpoints
tLZ(DQ) in Infiniium oscilloscope
Data Signal (DQ as Pin Under Test Signal)
Clock Signal (CK as Reference Signal)
.
Data Strobe Timing (DST) Tests
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U7233b

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