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7
Data Strobe Timing (DST) Tests
NOTE 15: tHZ and tLZ transitions occurs in the same access time as valid data transitions. These
parameters are referenced to a specific voltage level which specifies when the device output is no
longer driving (tHZ), or begin driving (tLZ).
device is no longer driving (tHZ), or begins driving (tLZ) by measuring the signal at two different
voltages. The actual voltage measurement points are not critical as long as the calculation is
consistent.
PASS Condition
The measured time interval from the point where the DQ starts to transit from high/low state to high
impedance state, to the clock signal crossing point should be within the specification limit.
Measurement Algorithm
1
2
3
4
5
6
7
8
9
10 The Histogram Window is required to cover the DQ signal from the high/low state to the moment
11 Setup the threshold value and measurement point for the DQ signal based on the histogram
12 Once all the points are obtained, proceed with the trigonometry calculation to find the point
13 Assign marker A for the clock signal crossing point while marker B for the data signal start to turn
14 Measure delta of marker A and marker B and this will be the test result.
15 Compare the test result against the compliance test limit.
Some designs do not have tristate at V
NOTE
scenario happens, as there is no significant point of where the driver has been turned-off.
Test References
See Table 11 - Electrical Characteristics and AC Timing, in the JEDEC Standard JESD79E.
86
Obtain the parameters and settings from the Configuration page.
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Chip Select (CS) option is only applicable if the user has selected "Yes" for the Verify Selected
Rank Only option in the Configuration page. It uses the CS-DQS for signal separation. Else, by
default, the DQS-DQ is used for signal separation.
Use the InfiniiScan feature with the Setup time and Hold time to find and capture the Read cycle.
If you have selected the CS option, skip the next step and go to step 9.
Search for the DQS preamble towards the right from the point where the Read cycle was
previously captured. The For loops, TEdge and Delta Time are used to search the preamble.
Once the preamble is located, call the "BinaryEdgeNormal" function, using Clock as the reference
to define the Histogram Window for the DQ signal.
it starts to turn off the driver into tristate.
result.
where the DQ starts to transit from high/low to the time when it turned off its driver into tristate.
off its driver.
Figure 30
shows a method to calculate the point when
(for example, 0.9V). This test is not guaranteed when this
REF
DDR1 Compliance Testing Methods of Implementation
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