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4
Single-Ended Signals AC Output Parameters Tests
Signals required to perform the test on the oscilloscope:
•
•
•
* Pin Under Test signal can be either one of the signals under the test definition.
Test Definition Notes from the Specification
Table 19
Low Power DDR SDRAM Electrical Characteristics
Parameter/Cond ition
DC Output High Voltage (IOH = -0.1mA)
PASS Condition
The maximum value for the high level voltage should be greater than or equal to the minimum
V
OH(AC)
Measurement Algorithm
1
2
3
4
5
6
7
8
9
10 Compare the test results against the compliance test limits.
Test References
See Table 8 - Low Power DDR SDRAM Electrical Characteristics, in the JEDEC Standard JESD79E.
58
Data Signal (DQ as Pin Under Test Signal)*
Data Strobe Signal (DQS as Supporting Signal)
Clock Signal - CK is required to perform pre-test to verify the DUT speed against user's speed
grade selection
value.
Calculate the initial time scale value based on the selected DDR1 speed grade options.
Pre-condition the scope settings. Verify the actual DUT speed against the user speed selection at
the Setup page.
Calculate the number of sampling points according to the time scale value.
Obtain sample or acquire signal data and perform signal conditioning to maximize the screen
resolution (vertical scale adjustment).
Perform signal checking on all the signals in-use in the measurement to ensure that it can be
triggered during the test. This includes Vp-p, Vmin, Vmax and Vmid of each signal.
Perform signal skew checking on the DQ-DQS to ensure that it can be triggered during the
Read/Write separation later.
Setup the required scope settings and histogram function settings.
Use the histogram Max value as the test result for V
When multiple trials are performed, the smallest value (worst case) among the trials will be used
as the test result for V
OH(AC)
Symbol
Min
VOH
0.9 * VDDQ
OH(AC)
.
DDR1 Compliance Testing Methods of Implementation
Max
Units
V
.
Notes
-
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