Thz(Dqs), Dqs High Impedance Time From Ck/Ck# - Test Method Of Implementation; Signals Of Interest; Test Definition Notes From The Specification - Keysight U7233A Testing Notes

tHZ(DQS), DQS High Impedance Time From CK/CK# - Test Method of Implementation

The purpose of this test is to verify that the time when the DQS starts driving (from tristate to high
state OR low state stage), to the clock signal crossing, is within the conformance limits as specified in
the JEDEC Standard JESD79E.
Figure 31

Signals of Interest

Based on the test definition (Read cycle only):
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•
Signals required to perform the test on the oscilloscope:
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•
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Optional signal required to separate the signals for the different Ranks:
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Test Definition Notes from the Specification

Table 34 Electrical Characteristics and AC Timing
AC Characteristics Parameter
DQ & DQS high-impedance time from CK/CK
AC Characteristics Parameter
DQ & DQS high-impedance time from CK/CK
DDR1 Compliance Testing Methods of Implementation
Method for Calculating Transitions and Endpoints
Data Strobe Signal (DQS as Pin Under Test Signal)
Clock Signal (CK as Reference Signal)
Data Strobe Signal (DQS as Pin Under Test Signal)
Data Signal (DQ as Supporting Signal)
Clock Signal (CK as Reference Signal)
Chip Select Signal (CS as additional signal, which requires an additional channel)
Symbol
Min
tHZ
Symbol DDR 400A (2.5-3-3)
Min
tHZ
DDR 333 DDR 266
Max Min Max
+0.7 +0.7
DDR 400B (3-3-3)
Max Min Max
+0.7 +0.7
Data Strobe Timing (DST) Tests
DDR 200 Units
Min Max
+0.7 ns
DDR 400C (3-4-4) Units
Min Max
+0.7 ns
7
Notes
15
Notes
15
87